CSE468: Very Large Scale Integration

5

Introduction to CMOS technology and circuit design; implementation of combinational and sequential logic; VLSI design methodologies; CAD tools for layout, simulation, and validation. Students design a VLSI chip using modern CAD tools.

CSE 370.

Digital Integrated Circuits, A Design Perspective (2nd edition), J. M. Rabaey, A. Chandrakasan, and B. Nikolic, Prentice-Hall, 2003.

Students will: 1. Understand the principles underlying transistor (especially MOSFET) operation. 2. Understand the static and dynamic behavior of physical (i.e. silicon) logic gates, including transistor sizing, time constants, loading and delays, fan-in and fan-out, interconnect, etc. 3. Understand the behavior of physical (i.e. silicon) sequential-logic circuits, including clocking (single and two-phase), clock skew, pipelining, memories and memory access, interconnect, etc. 4. Master the basics of integrated-circuit fabrication, including floorplanning, layout, interconnect, and processing. 5. Master the tools of custom IC design, including schematic entry, simulation (analog, static timing, dynamic timing), layout, DRC, and LVS. 6. Know about advanced topics, including MOS scaling, BJTs and differential (CML) logic, high-speed and low-power circuits, etc.

Transistor basics * Fermi levels and band diagrams * The pn-junction diode * The MOS transistor * Sub- and above-threshold MOSFET operation * Static and dynamic MOSFET behavior CAD tools for physical IC design * Schematic entry * Simulation and analysis * Physical layout * DRC and LVS to verify your design * Parisitic extraction * Switch-level timing simulation Inverters and pass transistors * Static and dynamic behavior * Noise margin, fan-in and fan-out * Time constants, logic levels, drive Static CMOS logic * Basic logic gates * Static and dynamic behavior * Time constants (RC), loading, fan-in and fan-out, delays * Transistor sizing Dynamic CMOS logic * Domino, CVSL logic * Dynamic behavior * Cascading logic stages Sequential circuits * Static latches and flip-flops * Dynamic latches and flip-flops * Registers * Merged logic * Clocking (single and two-phase) * Clock skew, delays, race conditions Chip design * Floorplanning * Power bussing, power and ground bounce * Interconnect and delays * Clocking and PLLs * Yield * Design margin * Pads Memories * Static RAM * Sense amplifiers * Address decoders * Dynamic RAM * Nonvolatile memories Arithmetic circuits * Adders * Multipliers Advanced topics * Copper, SOI/SOS, deep submicron * Technology scaling * Low-power design * Bipolar transistors, differential CML * High-speed circuits, controlled impedance lines

3 hours of lecture per week 3 hours of laboratory per week Final project including documentation and report

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