CSE370 Assignment 5
Distributed: 28 October 2000
Due: 3 November 2000
Reading:
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Katz, Chapter 4 (pp. 207-224).
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Katz, Chapter 5 (pp. 240-266).
Exercises:
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Draw schematics for two versions of a full-adder in DesignWorks. One should
be done using a half-adder as a sub-block and another without sub-blocks.
Make sure to read Chapters 7 and 8 of the DesignWorks manual that describe
how to create your own symbols as well as the tutorials. Turn in the schematics
for each type of full-adder and for the half-adder symbol. Simulate your
schematics. Verify that your designs are correct by trying all 8 input
combinations in each case. Turn in the timing waveforms as well.
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Construct a 4-bit ripple-carry adder using the full-adder implementation
from the previous problem (use the one built using the half-adder as a
sub-block). Turn in the schematic. To verify your design, use the "Hex
Keyboard" symbol in the "Primio" library to make it easier to input a 4-bit
number. Turn in the timing waveforms showing what happens when you have
"1111" and "0000" as the numbers to be added and you change the "0000"
to "0001". How long does it take the sum to get to the right value? Repeat
this experiment starting with "1010" and "0000" and changing the "0000"
to "0101". Explain the differences between the two cases.
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Repeat problem #2 but now construct a 4-bit carry-lookahead instead.
Use the same full-adder module from problem #1. Repeat the two simulations.
How much faster is the carry-lookahead adder in both cases? Explain thedifferences
with the result of problem #2. How do your circuits from problem
#2 and problem #3 compare in the total number of gates they use (remember to
consider gates in all subblocks)?
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Design a 8-bit carry-select adder for unsigned numbers. It should be designed
hierarchically at the schematic diagram level and include 3 instances of
the 4-bit ripple-carry adder module you created for problem #2. You'll
also need to include some multiplexers. Make sure that your 8-bit carry-select
adder also has a carry-out in case anyone would ever want to use it to
build a larger adder. Verify its operation for "11111111" + "00000001".
Turn in the schematic and simulation waveform.
Rationale:
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To compose hierarchical combinational circuits.
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To better appreciate the differences between ripple-carry, carry-lookahead,
and carry-select adders.
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