Implement the function Z = AB’C’D’ + A’B’CD’ + BD + A’C’D + ACD using the PLA provided below.

We can rewrite Z into a form similar to the 8:1 multiplexer equation:

Z = A'B'C'I₀ + A'B'CI₁ + A'BC'I₂ + A'BCI₃ + AB'C'I₄ + AB'CI₅ + ABC'I₆ + ABCI₇

Z = AB'C'D' + A'B'CD' + BD + A'C'D + ACD
Z =  (AB'C'D') +
        (A'B'CD') +
        (A'BC'D + A'BCD + ABC'D + ABCD) +
        (A'B'C'D + A'BC'D) +
        (AB'CD + ABCD)

The parentheses indicate related terms derived from the same original terms.  Then by regrouping, we obtain the canonical sum-of-products form:

Z =  A'B'C'D + A'B'CD' + A'BC'D + A'BCD + AB'C'D' + AB'CD + ABC'D + ABCD

This lets us easily complete the multiplexer design by assigning values of D or D' to the corresponding inputs.  Note that the only values for the inputs are D and D', 0 and 1 are not used for this example.

Extra credit: Implement the function yet again using the 3:8 decoder provided below and as few extra gates as possible.
 

The decoder can be used to form all the product terms of the inputs A, B, and C.  These terms can then be combined with D and D' to yield Z.  Starting with the equation for Z in canonical form we simply group all D terms and all D' terms using two OR gates, then AND in D and D', respectively, and OR these two parts together to form Z.  See the circuit below using notation for the large OR gates similar to PLA notation.

Z =  A'B'C'D + A'B'CD' + A'BC'D + A'BCD + AB'C'D' + AB'CD + ABC'D + ABCD
Z =  A'B'C'D + A'BC'D + A'BCD + AB'CD + ABC'D + ABCD + A'B'CD' + AB'C'D'
Z =  (A'B'C' + A'BC' + A'BC + AB'C + ABC' + ABC)D + (A'B'C + AB'C')D'