Below is the Verilog description of a finite-state machine.
(a) Derive its state diagram.
(b) State whether it is a Moore or Mealy machine.
(c) Describe the behavior of the state machine in one or two sentences?
(d) Derive its realization in terms of three positive edge-triggered D-flip-flops and some small gates.

module ShiftReg(Reset, X, Clk, Q0, Q1, Q2);
    input Reset, X, Clk;
    output Q0, Q1, Q2;

    reg QO, Ql, Q2;

    reg [0:2] state;

    `define s1 3'b100
    `define s2 3'b010
    `define s3 3'b001

    always @(posedge Clk) begin
        if (Reset) state = `s1;
        else begin
            case (state)
                `s1: if (X) state = `s2 else state = `s1;
                `s2: if (X) state = `s3 else state = `s2;
                `s3: if (X) state = `s1 else state = `s3;
        end
    end

    assign Q0 = state[0];
    assign Q1 = state[1];
    assign Q2 = state[2];

endmodule