CSE370 Assignment 6

Distributed: 28 April 2000
Due: 5 May 2000

Reading:

1. Katz, Chapter 6 (pp. 282-313).
2. Katz, Chapter 7 (pp. 329-337).

Exercises:

1. Construct a 4-bit carry-lookahead adder using your full-adder implementation from the assignment #5. Repeat the simulation with "1111" added to "0001" (changing from the previous value of "0000" so that the entire carry-chain is exercised). How much faster is the carry-lookahead adder? How many does it compare in gate count?
2. Construct a Verilog model for a 4-bit adder. Use the Verilog "+" operator to implement addition. Verify it using the same examples as for the last assignment. Make sure that your module includes a carry-out output for use in the next problem. Turn in the Verilog source for your module and the simulation waveforms.
3. Design a 8-bit carry-select adder for unsigned numbers. It should be designed hierarchically at the schematic diagram level and include 3 instances of the Verilog module you defined in the previous problem. You'll also need to include some multiplexers. Make sure that your 8-bit carry-select adder also has a carry-out in case anyone would ever want to use it to build a larger adder. Verify its operation for "11111111" + "00000001". Turn in the schematic and simulation waveform.
4. Implement the calendar subsystem we've done in class using Verilog. Create a module whose inputs are month and leap_flag and whose outputs are d28, d29, d30, and d31. Verify it using DesignWorks. Turn in your Verilog source.
5. Katz exercise 6.11 (a,b,c).
6. Katz exercise 6.14.

Rationale:

• To understand the implementation of addition in combinational logic networks.
• To lean the use of a hardware description language to design circuit blocks.
• To reinforce speed/area tradeoffs in combinational logic design.
• To begin understanding the basic building blocks of sequential circuits.