CSE370 Quiz 3 Solution (7 May)
 
  1. Design a 4-bit adder that adds a 4-bit 2s complement number to a 4-bit sign/magnitude number and produces a 4-bit 2s complement result. Your circuit must use four 1-bit full adders as the basic building blocks, but you may add any other logic you wish. Do not worry about overflow.


  2. The sign-bit of the sign/magnitude number (b3) is used to selectively complement the bits of the magnitude (b2, b1, and b0) as well as add 1 via the carry-in of the full-adder of the least significant bit (thus converting the sign/magnitude number into a 2s complement number.  This scheme also works correctly for both forms of 0 (0000 and 1000) in sign/magnitude notation.
     
     

  3. You are given the basic sequential circuit consisting of two cross-coupled NAND gates. Which input values (A and B) cause the state of the circuit to be set (Q = 1, Q' = 0)? Does this circuit have an input condition that should not be used and if so, what is it? Explain why or why not in 1 sentence.

  4. A = 0, B = 1 set the latch so that Q = 1 and Q' = 0.  The input combination A = 0, B = 0 should not be used as it sets both Q and Q' to 1 with unpredictable results (race condition) if the inputs are then switched to hold (A = 1, B = 1).  The analysis is analogous to that of the cross-coupled NOR gates done in lecture and in the text.


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