Collaboration Policy:

Unless otherwise noted, your group may collaborate with other CSE467 groups on the lab assignments. Collaboration means that you may discuss the experiments and make notes during the discussion, but you may not copy another group’s work when doing the experiments; you may not copy experimental results from another group; and you may not copy any part of another group’s lab report. In addition, every individual in a group must understand the experiments, must participate in the writeup, and should understand the results. Collaboration does not mean that one person may perform the experiments and another write up the results—all lab partners must share equally in all parts of the lab assignment.

Late Policy:

The lab assignments are due in one week, at the beginning of your lab section. Assignments handed in after lab will incur a 10% penalty; the penalty will increase by 10% for each additional day late.

In this lab will you will learn the following:

• Compile a design
• how to compile Verilog
• how to connect your design to the FPGA pins
• how to compile your desgn to produce a "bit file"

• XS40 Board
• the architecture of the XS40 board
• how to connect to the FPGA pins
• how to download a design to the FPGA

• Test and debug
• how to test the FIFO design using the logic analyzer

This lab has one handout:

1. XS40 documentation

The Foundation tools will compile your design when you click on the Implementation button in the Project Manager window. The result of this process (unless there are errors) is a "bit file". This is an object file that can be downloaded to the FPGA. After you have performed the implementation, you should take a look at the reports that Foundation generates. These can be found by clicking the Reports tab in the Project Manager. Pay particular attention at this point to the first three reports. We will learn a lot more about what happens during implementation, but for now we can treat it as a black box. By the way, we recommend that you not use the versioning feature of the tools. In fact, it is a good idea to delete the implementation data (in the Project Menu).

Note: The Verilog compiler (called FPGA Express) has already been run whenever you edited the Verilog file and you would have fixed any errors then.

The XS40 board contains a Xilinx 4010XL FPGA along with a microcontroller (which we will not be using) and a 32Kx8 SRAM (which we will use later). The schematic in the XS40 documentation shows how these three components are connected together. At this point, you do not have to understand these connections. We have already assigned the pins of the FPGA for you in the top-level schematic. (You might be interested which pins we chose.)

The key thing about the XS40 board is that the pins of the board around the periphery are each connected to the Xilinx chip pins with the same numbers. That is, you can connect to a Xilinx chip pin by just connecting to the protoboard connection for the board pin with that number. Be careful figuring out the numbers though!

The most important connection for the XS40 board is the GND connection - pin 52. You must connect pin 52 to the prototyping board GND. Failure to do so can result in a blown Xilinx chip ($40).

We will give you a chip (a 24-pin PLD) that will provide the test data for the FIFO implemented in the FPGA. To run this chip, first turn on Reset, then turn it off. The chip will generate random data to the FIFO as well as random Reads and Writes.

The pins of this chip are numbered from pin 1 to 24 around the chip in the usual way. Here are the pinouts of the test PLD:

Pin 1 - CLK (same clock as Xilinx chip CLK)
Pin 2 - Reset (same reset as Xilinx chip reset)
Pins 21-14 - DataIn[7:0] Input data to the FIFO
Pin 22 - Write signal for the FIFO
Pin 23 - Read signal for the FIFO

You could provide the reset input by a simple wire that you connect to Vdd or GND. However, it is a lot better to use a switch, which you should have in your DesignKit. A switch is made using contacts that are connected or disconnected. The problem with switches is that when the contacts are connected, they bounce, which means you get multiple edges instead of one clean edge. We will fix this problem with a simple circuit and a 3-terminal push-button switch.

Find a pushbutton switch in your Design Kit that has three terminals. One of these terminals is a "common" terminal while the other two are "normally-closed" (NC) and "normally-open" (NO). When the switch is not being pushed, it is in the open state. In this state, the common terminal is connected to the NC terminal. When the switch is being pushed, the common terminal is connected to the NO terminal. Use the multimeter to determine which terminal is which by measuring the resistance between terminals. (We’ll show you how to use a multimeter if you haven’t used one.)

We can debounce a switch by using a latch and using both the normally-open and normally-closed terminals of the switch as shown in the figure below. The first contact of the switch will cause the latch to change state. Then, even if the switch bounces, the latch will stay in the same state. Use a 74LS00 chip to implement the switch debounce circuit.

Once you have the circuit connected, test it to make sure that it works.

Before you run the circuit, you will need to connect up the logic analyzer so that you can see whether the FIFO is working properly. You will need to sample all the FIFO interface signals: DataIn[7:0], DataOut[7:0], Read, Write, Empty and Full and this will take 3 sets of 8 wire leads and two cable headers. Connect your wire leads so that it will be easy to unplug them from the logic analyzer and then plug them in again later. You can keep the wire leads plugged into the board until you are finished with them.

You are now ready to try out your circuit by downloading the Bit File (FIFO.bit) for your design. Before you do this you must connect power to both the protoboard and the XS40 board, and connect the PC parallel port cable to the XS40 board.

1. Plug in both the protoboard and XS40 power supplies.
2. Plug in the PC parallel port cable
3. Find the FIFO.bit file in your project directory. In a DOS window, download this file using the following command: xsload fifo.bit
4. Initialize your circuit by hitting the reset button.

After you have setup the data signals, set up the trigger to trigger on the reset signal going low. Now capture the data when you press and release the reset button. Look at the signals and determine whether the FIFO is behaving correctly. Print out one (or more) windows that show all the following cases:

• Normal operation - indicate where data is written to the FIFO and where the same data is read out of the other end

• Reading an empty FIFO - show that the FIFO behaves

• Writing a full FIFO - show that the FIFO behaves, and allows the write if there is a read happening at the same time