N-bit Register with Asynchronous Reset

module regN (reset, CLK, D, Q);

input reset;

input CLK;

parameter N = 8; // Allow N to be changed

input [N-1:0] D;

output [N-1:0] Q;

reg [N-1:0] Q;

always @(posedge CLK or posedge reset)

if (reset)

Q = 0;

else if (CLK == 1)

Q = D;

endmodule // regN

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