Verilog FSM - Reduce 1s example
parameter zero = 0, one1 = 1, two1s = 2;
module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg [1:0] state; // state register reg [1:0] next_state;
// Implement the state register
always @(posedge clk) if (reset) state = zero; else state = next_state;
Change the first 1 to 0 in each string of 1’s
- Example Moore machine implemenation