Mealy Verilog FSM for Reduce-1s example

7

module reduce (clk, reset, in, out); input clk, reset, in; output out; reg out; reg state; // state register

reg next_state; parameter zero = 0, one = 1;

always @(posedge clk)

if (reset) state = zero; else state = next_state; always @(in or state) case (state) zero: begin // last input was a zero out = 0; if (in) next_state = one; else next_state = zero; end one: // we've seen one 1 if (in) begin next_state = one; out = 1; end else begin next_state = zero; out = 0; end endcaseendmodule

Previous slide

Next slide

Back to first slide

View graphic version