CSE467: Advanced Logic Design

Carl Ebeling, Winter 2000

Approximate Schedule

Week   Date    Lecture

 1   Jan 3-7   Review of combinational/sequential logic
 2   Jan 10-14 Review of FSMs, Xilinx tools
 3   Jan 19-21 Datapath/Control design, FIFO
 4   Jan 24-29 Designing with Verilog; VGA Interface
 5   Jan 31-   Memory design & interfacing, FPGA architectures
     Feb 4
 6   Feb 7-11  Logic synthesis for FPGAs: mapping, place and route; 
               multi-level logic synthesis
 7   Feb 14-18 Logic families, physical realities, high-speed circuits
               [Guest lectures: Chris Dioro]
 8   Feb 23-25 FPGA systems;  Systems Design overview
               [Guest lectures: Scott Hauck, Larry Arnstein]
 9   Feb 28-   Asynchronous inputs, metastability, clock skew, timing
     Mar 3
10   Mar 7-11  

Tentative Lab Schedule

Week    Date   Lab

 1    Jan  6   Oscilloscopes
 2    Jan 13   Intro to Xilinx Foundation
 3    Jan 20   Logic Analyzers
 4    Jan 27   XS40 board and FIFO
 5    Feb  3   VGA/Memory Interface, simple image display
 6    Feb 10   Dual-port memory interface, line-drawing
 7    Feb 17   Project (Double-buffering, display lists)
 8    Feb 24   Project (Simple transformations)
 9    Mar  2   Project (Bells & Whistles)
10    Mar  9   Projects Done