CSE467: Advanced Logic Design

Week   Date  Lecture

 1   Jan  5  Course overview; Review of combinational logic.

             Chapter 2.1-2.9

     Jan  7  Review of combinational logic; Verilog for combinational logic; Minimization.

             Chapter 2.10, 4.1-4.4

     Jan  9  Factoring and multi-level logic synthesis.

             Chapter 4.5-4.8

 2   Jan 12  Factoring & Shannon decomposition.

             Chapter 4.5-4.8

     Jan 14  Factoring; Review of number systems & arithmetic. HW 1 due

             Chapter 5.1-5.3

     Jan 16  Fast adders: Carry-lookahead and carry-select. Quiz

             Chapter 5.4-5.5

 3   Jan 19  Holiday

     Jan 21  Multiplication; Floating-point. More Verilog;

             Chapter 5.5-5.7

     Jan 23  System building blocks: Muxes, decoders, encoders. More Verilog. HW 2 due

             Chapter 6.1-6.6

 4   Jan 26  Review of registers, synchronous methodologies, timing constraints.

             Notes (Chapter 7)

     Jan 28  Review of FSM design; Mealy vs. Moore

             Chapter 8.1-8.3

     Jan 30  Verilog for FSMs. Quiz

             Chapter 8.4

 5   Feb  2  Guest lecture (Rob Duisberg) – sound synthesis

     Feb  4  Datapath/Control model of computation

     Feb  6  Datapath/Control design

 6   Feb  9  Scheduling and time-multiplexing

     Feb 11  Pipelining and Retiming

     Feb 13  C-slowing. FPGA Architectures. Quiz

 7   Feb 16  Holiday

     Feb 18  Guest lecture – Place and route for FPGA systems

     Feb 20  Guest lecture (Chris Diorio) – high-speed circuits

 8   Feb 23  Guest lecture – printed circuit board design

     Feb 25  Misc. FPGA topics

     Feb 27  Xilinx FPGA architecture. Quiz

 9   Mar  1  Xilinx FPGA architecture

     Mar  3  Register parameters.  System clocking

     Mar  5  Asynchronous inputs, metastability, clock skew

10   Mar  8  Communication: serial/parallel.  Design problem

     Mar 10  Design problem

     Mar 12  Review. Quiz

March 15-17 – Project interviews

Thursday, March 18, 8:30-10:30  Final Exam

Lab Time and Place: TuTh 2:30-5:20 – Allen 590

Week    Date   Lab

 1    Jan  6   Discrete parts, oscilloscopes

 2    Jan 13   Discrete parts, 7-segment decoder

 3    Jan 20   Virtex1000 board setup and compilation; Keypad to 7-segment display

 4    Jan 27   Virtex1000 board; Keypad to LCD display

 5    Feb  3   Audio board; Wavetable sound synthesis

 6    Feb 10   Project

 7    Feb 17   Project

 8    Feb 24   Project

 9    Mar  2   Project

10    Mar  9   Projects Done

ebeling@cs.washington.edu