UW CSE
Autumn 1999
CSE467 Advanced Digital Systems Design
Instructor: C. Diorio

Homework Set 3 
DUE: Oct 22,1999, 9:30 am

Collaboration Policy:
Unless otherwise noted, you may collaborate with other CSE467 students on the homework assignments. Do not look at homework or exam solutions from previous years. You must spend at least 15 minutes working on a problem before seeking assistance. Collaboration means that you may discuss the problems and make notes during the discussion, but you may not look at other student’s work when writing up your homework. Your homework represents your own work—the homework must show that you understand the material and have worked as an individual on every problem. You may not divide up the task of doing the problem sets in the interpretation of collaboration. You may discuss lecture material with anyone.

Late Homework Policy:
The weekly assignments are due at the beginning of class. Assignments handed in after class will incur a 10% penalty; the penalty will increase by 10% for each additional day late.

Reading:
Review Katz, Chapter 8

Please show all of your work, and remember, your solutions must be legible. The points for each problem are noted on the problem statement.

1. (5 pts) Katz 6.22
 

2. (10 pts) Design a 3-bit counter that counts in the sequence 0, 2, 6, 4, 5, 7, 3, 1. Draw a state transition table, encode the next-state functions (minimizing the logic), and draw circuit schematics for designs using (a) D flip-flops and (b) T flip-flops.
 

3. (10 pts) Katz 8.14. Your state diagram should have 8 states. Also draw a state transition table, encode the next-state functions (minimizing the logic), and draw a circuit schematic for your design using D flip-flops.
 

4. (10 pts) As described in lecture, a one-hot state machine has a flip-flop for each state. This makes designing a one-hot state machine fast and easy—you can read the next-state logic directly off the state diagram or state-transition table. Each next-state function uses only the active predecessor state and the machine input, and there is one product term for each arc of the state diagram.

5. (5 pts) Calculate the MTBF of the synchronizer shown below, assuming a clock frequency of 25MHz and an asynchronous input with a 1MHz transition rate. Assume that the setup time and propagation delay for the 74ALS74 are both 10ns.