UW CSE
Autumn 1999
CSE467 Advanced Digital Systems Design
Instructor: C. Diorio

Lab # 4
DUE: In one/two weeks, at 1:30 pm

Collaboration Policy:
Unless otherwise noted, your group may collaborate with other CSE467 groups on the lab assignments. Collaboration means that you may discuss the experiments and make notes during the discussion, but you may not copy another group’s work when doing the experiments; you may not copy experimental results from another group; and you may not copy any part of another group’s lab report. In addition, every individual in a group must understand the experiments, must participate in the writeup, and should understand the results. Collaboration does not mean that one person may perform the experiments and another write up the results—all lab partners must share equally in all parts of the lab assignment.

Late Policy:
The lab assignments are due as described in the schedule (at the end of this document), at the beginning of your lab section. Assignments handed in after lab will incur a 10% penalty; the penalty will increase by 10% for each additional day late.

Overview:
The purpose of this lab is to give you experience using Verilog to specify finite state machines. When you have completed this lab, you will know how to:

Include Verilog components in your schematics 
Synthesize the Verilog components
Simulate and debug sequential circuits Although you will continue working in teams, for this lab each person must design their own personal FSM to write their name on an LCD display.

The lab:
Answer all the questions in this handout in your lab writeup. Show all of your work, and remember, your solutions must be legible. This lab is worth 40 points.
 

Part 1: Design an LCD Interface

In your DesignKit there is an LCD display that can display two lines of 16 characters each.

You control this display using data and control lines, as described in detail in the next section. Your first job is to design a simple LCD interface, as shown in the following figure, that you will use for the remainder of the course. Your LCD interface accepts a Strobe signal, some additional command signals, and a set of data inputs. Strobe is an input that tells your circuit to display a new character. When Strobe goes from low to high, your circuit should read the character on the data lines and display it on the LCD display. Ready is an output that tells you when the interface is ready to accept another character. You must wait until Ready is asserted before asserting Strobe. When your interface receives Strobe, it should deassert Ready until it has finished displaying the character. Strobe and Ready form a handshake protocol that is very common in interfaces. A user waits for Ready to assert, responds by asserting Strobe, then waits for Ready to be deasserted by the LCD interface (indicating that the interface has seen the Strobe) before deasserted Strobe. The user then waits for Ready to assert again, before starting a new transaction. This handshaking is called an asynchronous protocol because it makes no assumption about how slow or how fast the interface is. Command information is encoded in two bits as follows: 00 – Write a character to the screen
01 – Clear the screen
10 – Backspace
11 – Home Your LCD interface samples the command signals when Strobe asserts, and performs the appropriate actions based on the command. If the command is to write a character to the screen, then the 8 data lines will specify what character to write. The encoding is not ASCII—see the LCD datasheet for the encoding details. Note that if you choose not to use Backspace or Home, you can tie the high order bit of the command inputs to 0.

 

Part 2: Design an FSM to Write Your Name on the LCD Display

Design an FSM (called an LCD tester) that sends commands to your LCD interface, to write your name on the display. This FSM should have a reset and a go input. When go is asserted (use a debounced switch), the FSM should display your name and then quit. Reset should clear the display. Each team member should design their own FSM, that displays their name on the display.

Notes: The LCD Screen

Your interface circuit converts a simple interface protocol to the somewhat more complicated protocol used by the LCD driver. The LCD accepts both instructions and data on its Din lines; whether it interprets the inputs as instructions or data depends on the value of the RS signal. For character write operations, set RS to 1. To execute a command, set RS to 0. The table below shows the instructions you will use. The first four instructions initialize the display for our configuration (a 1 line by 16 character display). Your LCD interface must issue these instructions whenever it resets.

Operation RS R/W DB7...DB0
Clear Display 0 0 0000 0001
Function Set 0 0 0011 00**
Display ON 0 0 0000 1100
Entry Mode Set 0 0 0000 0110
Write Character 1 0 DDDD DDDD
Backspace 0 0 0001 00**
Return Home 0 0 0000 001*
Read Character 1 1 DDDD DDDD You must satisfy additional timing constraints when you write information to the display. Basically, the LCD display samples RS on the rising edge of enable (E), and samples the data (DB) on the falling edge of E. To keep things simple, you should assume that the setup and hold time for RS should be one clock cycle before and after the rising edge of E, respectively. Assume a similar situation for the falling edge of E. The only other relevant timing information is to allow 1.6ms for the display to clear (the internal controllers take time to enter 0s into the internal memory of the display unit).

Because you never need to read, you can tie the R/W control line directly to GND. The easiest way to write is to assert the enable signal (E) for one clock cycle during which both RS and data are stable. The signals that your LCD interface generates should look like:

You must ensure that the input data are stable when writing the display (not a problem, because the Ready signal tells you that the LCD interface is busy during writing). Because the Enable signal clocks data into the display, it should be hazard-free (no spurious glitches). The easiest way to ensure this is to make it the output of a flip-flop.

You need to connect Vdd (+5V) and GND to the LCD display, and also connect the VO input to a potentiometer to provide a voltage between 0V and +5V. The potentiometer voltage sets the display contrast. We will give you the potentiometer—you will need to use a multimeter to figure out the terminals and how it works. The figure below (copied from the LCD documentation) shows how to make the connections.

Details, Details, Details...

A good part of designing a circuit is defining the problem. Most problem descriptions are incomplete or ambiguous. One of your tasks when designing is to turn an incomplete description into a precise specification. Before you begin the design, ask yourself what is missing and write down as precise a specification as you can. Hand in a written design specification along with your circuit design for this lab assignment.

NOTES:

1. Don't forget to provide a reset input to both state machines.

2. The XESS board runs at 12MHz, which is too fast for the LCD display. The data sheet indicates that the display takes 40µs to execute a command (except for Home and Clear, which take 1.6ms). We could use counters to delay for ~400 cycles between issuing commands. Instead, we will divide down the FPGA clock so that it runs at 100kHz instead of 12MHz. Construct a 7-bit counter and connect the internal clock to the counter's high-order bit. Put this counter inside the FPGA. Put a BUFG on the counter output to buffer the internal clock signal. For the Home and Clear commands, you need to wait 1.6ms before asserting the Ready signal, so you will have to do some counting.

 Entering and Simulating your Design:

Divide each design into reasonably-sized components, such as registers and counters and combinational logic. Draw a top-level schematic for your design. You can use Verilog to specify both your sequential (e.g. FSM) and combinational (e.g. code converter) components. You can also use library and LogiBlox components.

You should simulate your circuit, and then download it to the XESS board. Use XESS board pins 8 and 9 for your input switches (reset and go) and pins 18, 19, 20, 23, 24, 25, 26, 27, 28, 29, 30 to connect to the LCD display. In addition, include the following connections in your top-level schematic. Doing so will disable the microcontroller on the XESS board so that it doesn't get in the way.

Please be very careful with the boards—handle them carefully and make sure that GND is connected between the protoboard and the XESS board.

Schedule:

Turn in within one week:

1. Design documentation: Whatever notes that we need to understand your design. Remember, you are responsible for making sure we understand your design. If we can't understand it, we can't grade it.
2. Printout of all schematics
3. Printout of all Verilog modules
4. Printout of simulation script, log file and waveform
5. Signature of TA Turn in within two weeks: 1. Completed and working circuit
2. Signature of the TA to show that you demonstrated the circuit and that it worked correctly. Don't procrastinate! Getting the LCD circuit to work properly can be tricky. Use the logic analyzer.