Week5, Lecture3: Verilog synthesis
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Table of Contents
Verilog synthesis
A few requirements for CSE467...
Synthesis
Synthesis in CSE467
Logic synthesis
Synthesis examples
Conditional statements
case is a priority encoder
parallel_case and full_case
Arithmetic synthesis
Sequential synthesis and Xilinx
The Xilinx 4000 CLB
Bit widths in arithmetic expressions
Memories
Tristate buffers
Verilog: What we skipped...
Author:
Chris Diorio
Email:
diorio@cs.washington.edu
Home Page:
http://www.cs.washington.edu/education/courses/467/99au/