|====================================================================
|================== Simulation Script Template File =================
| This is just a sample file to help get you started.  Feel free to
| modify this file as you see fit.  For a more detailed script file,
| see the "Complete Script Example" provided in the Xilinx Macro
| Assistant (in the Script Editor).
|====================================================================


|===============SETUP===============

|-----Simulator Settings-----
delete_signals    | delete any existing waveforms in the window
clpr sim_out.out  | clear the output file
logfile ON        | turn on logging
restart           | restart to time zero

|-----Vectors-----
| Assign names to groups of related signals here.  Also, you can specify
| the radix/base in which to display these signals.



|-----Watch Statements-----
| List any signals you want to see in the waveform viewer, or which you
| want to output to a file.



|-----Clock Settings----- 
| Setup various clock signals.  Also, can specify their shape and timing.
stepsize 50.0ns
clock CLOCK 0 1



|===============SIMULATION===============
|
| The following commands will be useful:
|   'assign' - to assign values to pins/wires (use 'release' to stop
|                driving a signal)
|   'check'  - to make sure the expected values appear on pins/wires
|                (a list of any errors will appear in your log file)
|   'cycle' (or 'sim' or 'run') - to progress through the simulation
|
| You can also use 'print FILENAME' if you want to output the value of all
| 'watch'ed signals to a given file.


|| good idea to toggle SimGlobalReset to
|| make sure the design is initialized
h SimGlobalReset
cycle 3
l SimGlobalReset
cycle