CSE467: Advanced Logic Design

Carl Ebeling, Winter 1999


Lab 4

Using the Logic Analyzer

Distributed: Feb 3
Part 1 Due: At the end of Lab
Part 2 Due: With Lab 3

You should do this lab assignment as a project team.

The Logic Analyzer

Debugging sequential circuits is much more difficult than debugging purely combinational circuits. This is because you need to see the history of a sequential circuit to understand whether it is working correctly. The logic analyzer samples the values of signals that you want to see and displays these values using a waveform display similar to the one you get in a simulator. This way you can debug your circuit by seeing where things go wrong. The logic analyzer is fast enough to capture signal values even when the circuit is running at full speed.

The idea of a logic analyzer is fairly straightforward. However, it can be pretty complicated setting it up to do what you want. In the accompanying handouts, we have copied a section on logic analyzer concepts and some (not all!) of the manual for the Tektronix 1230 logic analyzer. There is more complete documentation in the lab as well.

You may find using this logic analyzer confusing at first, so we suggest you read carefully pages 7-9 of section 1 which covers general information about using the logic analyzer. You should also read the rest of this section, but some of the information will not make sense until you actually try to use the logic analyzer. The next step is to try out the logic analyzer by going through the exercises in the two handouts. The best way to learn is to try things out and ask questions if you don't understand something. Consultants will be standing by.

The two handouts contain two exercises which rely on a test card (available in the lab) that contains a simple counter circuit. The first exercise covers asynchronous operation which uses a free-running internal clock to sample data. In this mode, the signals are sampled at a clock frequency that you define using the logic analyzer. If you choose too slow a clock, you will not see all the values. If you choose too fast a clock, then you won't be able to sample enough of the waveform before you run out of memory. The idea is to oversample (multiple samples per clock edge) enough so that you can see all the values on the signal. Try out different clock speeds to see how this works.

The second exercise covers synchronous operation, which uses a clock that is part of the circuit to sample data. This makes sense when you want to see the values of signals precisely at the active edge of the system clock, which is where they really matter. Since you are sampling exactly where you want to, you'll be able to avoid oversampling and thus be able to sample a faster system, and you'll be able to collect a longer history into the logic analyzer's memory.

After you have done these two exercises, use the logic analyzer to observe the signals that your LCD interface provides to the display. First use asynchronous operation to sample the signals, using a reasonable clock and something suitable as a trigger. Next, use synchronous operation.

Hand In:

Part 1: (Due at the end of lab) Demonstrate your mastery of the logic analyzer on the two exercises with the test card.

TA Signature: _________________________

Part 2: (Due with your Lab 3 turnin) Use the logic analyzer to capture the waveforms that your LCD interface sends to the display and show this to the TA.

TA Signature: _________________________


ebeling@cs.washington.edu