Adding Constraints to your Xilinx Project

Overview

This document describes the basics of adding timing (and possibly placement) constraints to Xilinx Foundation projects.

References

The Xilinx Documentation Viewer found in Programs->Xilinx Foundation Series can be used to find all this information and more. You should look at Xilinx Books -> Foundation Series User Guide -> Appendix B: Foundation Constraints.

If you would like a web version you can look at the Xilinx online documents, and in particular Appendix B: Foundation Constraints.

Basics

First of all, here are three useful things to keep in mind (this may not be new to you):

The default time unit is in nanoseconds
You may need to reference nets in lower levels of your hierarchy. This is done using the forward slash, "/", much like a Unix path. Make sure you use instance names and not the macro names themselves. So for example H3/PADHSYNC would refer to the horizontal sync output in the VGA project (where H3 is the instance of VGACONTROL8).
It is a good idea to label nets to show their logical grouping and make it easier to use wild cards. Wild cards are a good way to quickly apply constraints to a number of nets. Put the more general label first. For example, a memory controller might have nets RAMPAD_OE, RAMPAD_WE, RAMPAD_ADDR[9:0], and RAMPAD_DATA[7:0] which could all be referenced by RAMPAD*.

Constraints can be added in a number of different ways. One common way is using the .ucf file (user constraint file). Pin assignment is one form of constraint that you should already be familiar with. You can also specify many other types of constraints in the .ucf file. Constraints can also be specified in your schematic but if you mix the two methods it is important to remember that the .ucf file always overrides other constraints.

PERIOD is a good general purpose constraint. It insures that all synchronous signals propagate within the clock period (respecting setup times). You would do this by including

NET CLK PERIOD = 50 ;

in your .ucf file, where CLK is the label on your clock net and the clock frequency is 20MHz (period=50ns). If your design has more than one clock you will need more than one of these lines. Obviously you may need to specify more specific timing constraints, most especially if time critical signals are connected to external devices.

More Details

Not Done... To Do:

FROM:TO timespecs
Layout constraints: optimize for speed switch
Refer to Path Exceptions for specifying different speed pads.