# Author: Hannah C. Tang (hctang@cs) # # Makefile for Project 3 ### Variables ### CXX = /uns/bin/g++ # The standard g++ compiler is broken. Do NOT use it CXXFLAGS = -Wall -ansi -g -fno-implicit-templates # Compiler flags TARGET_NAMES = pq-test # You can add more executables here ### Rules ### # The first target in a Makefile is the default. That is, a simple "make" # at the command line will build the "all" target for this Makefile. # Remember the general syntax for rules in a Makefile is: # : # # # ... # ## This makes everything all : $(TARGET_NAMES) ## These rules make the pq-test program # This executable depends on object code generated from PriorityQueue-test.cc # and the templated code generated by the instantiation file. This line # builds (it does not compile) the pq-test executable # The $@ variable is the name of the target; the $^ variable is # list of all the dependancies pq-test : PriorityQueue-test.o BinaryHeapInst.o $(CXX) $(CXXFLAGS) -Wl,-rpath,/uns/lib -o $@ $^ # This line compiles the object code. It does not build the executable (see # above for the build line) The $< variable is the name of the # *first* dependancy PriorityQueue-test.o : PriorityQueue-test.cc IPriorityQueue.hh BinaryHeap.hh $(CXX) $(CXXFLAGS) -c $< # This line compiles the object code. It does not build the executable (see # above for the build line) The $< variable is the name of the # *first* dependancy BinaryHeapInst.o : BinaryHeapInst.cc IPriorityQueue.hh BinaryHeap.hh BinaryHeap.cc $(CXX) $(CXXFLAGS) -c $< ## You can add rules for creating more executables below # This rule is a fake target -- that is, it doesn't generate any object # files; rather, the "make clean" command will execute the following rm # command (which cleans out your old object files and executable). clean : rm -f *.o *~ $(TARGET_NAMES) # And .... as a reward for reading through this entire Makefile, here is # is some information on pattern rules! =) # # Quoth Evgeny Roubinchtein (evgenyr@cs.washington.edu): # # > You could also use "patten rules" to tell 'make' how to produce a # > .o given a .cc. You wouldn't then have to write rules like: # > # > FOO.o : FOO.cc # > $(CXX) $(CXXFLAGS) -o $@ $^ # > # > for each .o you want to produce. # > # > Often, people also use automatic dependency generation with pattern # > rules. The sample Makefile Justin Husted has written (in /uns/examples) # > uses pattern rules and automatic dependency generation. # > # > Pattern rules are documented here: # > http://www.gnu.org/manual/make-3.79.1/html_node/make_100.html#IDX828 # > # > Automatic dependency generation is documented here: # > http://www.gnu.org/manual/make-3.79.1/html_node/make_44.html#IDX259 # # Thanks, Evgeny!