Active-HDL
- Tips, Hints, and Reference
Active-HDL is an
industrial-strength design tool. Like any tool, used in the right way, it
is very powerful and productive; but there are certain and quirks and idiosyncrasies
which, if ignored, will lead to hours - yea days - of frustration. This
page gives guidelines and tips for using the tools so that you don't run into
problems. They are listed in section in decreasing order of importance.
If you know something that should be included here, please mail it to us and we will add
it.
Rules to Always Follow:
·
Keep
it simple and don't stray from straightforward, proven ways of doing
things. Don't expect the tools to do things the way you think they should
be done. Don't fight the tools, go with the flow. The tools always
win.
·
Save
often; this should be obvious.
·
Run
Check-Diagram often, at least before
you compile. This will point out
problems that can cause you hours of frustration.
·
Pay
attention to warnings. At least
understand what they are before you ignore them.
·
Compile often. If a design file has been compiled before,
Active-HDL will often run with the old version even if the source code has been
changed since you last compiled.
·
Always
choose Verilog whenever Active-HDL asks you to choose a hardware description
language. CSE 370 will not use VHDL or
any other of Active-HDLs options at any point.
·
Always
make new designs with design flow. This matters much more later once you are
using the FPGA, but get in the habit.
·
Make
a Local Copy of a file when your add
it to a design, unless you really know what you are doing.
Things to Never Do:
·
Never
start the name of a file with a numeric character (0-9). If you do, you will probably need to replace
it with a new file and move the contents.
This is a serious problem with Active-HDL.
·
Don’t
try to rename a file. Instead create a
new file and copy the contents over.
·
Never
name two files the same name, even if one is a Verilog source file and one is a
.bde, they will both be compiled into modules with the same name.
·
Never
use manual input stimulators (for example clock stimulators) and a test fixture
to drive inputs at the same time. This
will cause very strange and incorrect simulation behavior.
General Troubleshooting:
If Active-HDL is acting strangely
and/or you think your design should be working but it isn't, you can try these
steps in addition to asking a TA or SLA for help.
1. Make sure you haven't done
anything under the "Things to Never Do" section above.
2. Make sure you ran what you
thought you did. Check your top-level.
3. Run Check
Diagram to ensure that
there are no small wiring bugs or other non-obvious problems in your
schematic. Active-HDL's schematic editor
often makes disconnections in your wiring very difficult to see.
4. Click Compile-All to ensure that your most recent
changes were all reflected in the compiled design Active-HDL is running.
5. Right-click the library with the
same name as your design and choose Clear Simulation
Data. Then Compile-All to reset your compiled design.
6. Save your work and restart
Active-HDL. Using an Active-HDL session
for more than an hour is asking for trouble.
7. In
Schematic Editor:
·
Each schematic has an associated symbol (in the Symbols Toolbox) that you
use to make hierarchical schematics. However, changes to the schematic or
to the symbol are not reflected automatically in the other. Here's what
you have to do: Right-click on your symbol, and select "Compare
symbol with contents...". This will tell you if there has been a
change and it will ask you whether you want to change the schematic or the
symbol. Usually you want to change the symbol because of a change you
made to the schematic. Presto, things are fixed.
·
You can change the symbol for a component by right-clicking and using the
"Edit symbol in separate window" option. (Don’t use this to fix
the above problem.)
·
You should always name your busses – Active will often get the right
size, but will sometimes make a mistake.
This also makes it easier to debug.
·
If you cannot compile, or the option to set a module as top level seems
to be missing
Check that you are working with
the active design. The design that is
current active is in boldface in the file-browser tab. To make a design active, right-click it and
select Set as Active Design.
·
If the probes that show the values of wires in your schematic whenever a
simulation is running have gone missing:
Click Diagram->Probes->Add
Probes.
·
If a schematic (.bde) file name italicized and won't compile, it probably
does not have a target language:
Close the file first (important),
then do [Design->Change Target HDL] and choose Verilog. Ignore the
warning. It may also indicate that the file is not part of the
compilation: Right-click on it and [Include in
Compilation]. If the schematic editor insists on creating
block diagrams with the name italicized, use the Wizard instead to create a
file.
(Restarting Active-HDL usually solves this problem.)
·
To add wire-stubs to all pins of a symbol quickly, right-click and select
"Add-Stubs".
Simulator:
·
If you cannot add ports to the waveform:
Make sure that you have
initialized a simulation.
·
If the waveform does not seem to make sense:
Click Zoom-to-Fit (a button on the waveform viewer
toolbar) to zoom out to the entire waveform then zoom in to the desired region.
·
Stimulators only work from the waveform window. To watch the
signals in the block diagram while using stimulators, detach the waveform
window and position it so that both the waveform and block diagram windows are
visible. Run the simulation from the waveform window using F5 and the
stimulators while watching the signals in the block diagram window.
Synthesis:
·
If you get:
# Error: Path to Quartus
<number> not found. Specify the path to the vendor tool in the Flows
-> Integrated Tools category of the Preferences window.
Click Tools->Preferences.
In the list on the left, expand Flows under the Environment category. Select Integrated Tools.
Make sure HDL Synthesis is set to Altera->Quartus
Synthesis and Implementation <number>.
·
If synthesis completes successfully but does not generate a .sof file:
Go to the Design
Flow tab and click Synthesis
& Implementation Options. Go to the Compilation tab and make sure that the 2nd,
4th, and 6th checkboxes (not radio buttons) are checked. The 4th (Run Assembler
During Compilation) ensures your .sof is generated.
·
(Advanced) If you want more detailed compilation output out of the
simulator:
Select GUI rather than Batch for the compilation mode under Synthesis
& Implementation Options->Main