CSE370 Assignment 6
Distributed: 6 November 2000
Due: 15 November 2000
Katz, Chapter 6 (pp. 282-313).
Katz, Chapter 7 (pp. 329-345, 352-356).
Construct a Verilog model for a 4-bit adder. Use the Verilog "+" operator
to implement addition. Verify it using the same examples as for problem
2 of assignment 5. Make sure that your module includes a carry-out output
for use in the next problem. Turn in the Verilog source for your module
and the simulation waveforms.
Katz exercise 6.10 (b, c).
Katz exercise 6.12 (a, b, c, d, e) and explain each of your answers with
a sentence or two.
Show how to implement a T-flip-flop starting with a D-flip-flop and a few
Using just basic D flip-flops and combinational logic (rather than the
TTL 74194 part), design a 4-bit register that implements the shift register
subsystem in Katz problem 7.3. Draw a DesignWorks schematic that
uses four identical sub-cells. Feel free to use an 8:1 multiplexer
in your cell design.
file for calendar application from the first week of the class.
To learn the use of a hardware description language to design circuit blocks.
To begin understanding the basic building blocks of sequential circuits.
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