There are many possible solutions to this assignment. One is provided here to serve as a single example.
module ChkSumGen(Ein, LdChkSum, Op0, Op1, OE0, OE1, OE2, OE3, Eout, Clk, Reset);
input Ein;
output LdChkSum;
output Op0;
output Op1;
output OE0;
output OE1;
output OE2;
output OE3;
output Eout;
input Clk;
input Reset;
reg LdChkSum;
reg Op0, Op1;
reg OE0, OE1, OE2, OE3;
/* Internals */
reg [7:0] state;
reg [7:0] next_state;
/* State encoding {LdChkSum, Op1, Op0, OE0, OE1, OE2, OE3, Eout} */
`define START 8'b00000000 /* wait for enable */
`define CHK3 8'b11000010 /* move first nibble into chksum register */
`define CHK2 8'b10000100 /* add second nibble to chksum */
`define CHK1 8'b10001000 /* add third nibble to chksum */
`define CHK0 8'b10010000 /* add fourth nibble to chksum */
`define ENABLE 8'b00000001 /* enable next block and wait until Ein goes low */
/* State flip-flops with reset */
always @(posedge Clk) begin
if (Reset) begin
state = `START;
end
else begin
state = next_state;
end
end
/* Next state logic */
always @(Ein or state) begin
case(state)
`START: begin
if (Ein) next_state = `CHK3;
else next_state = `START;
end
`CHK3: begin
next_state = `CHK2;
end
`CHK2: begin
next_state = `CHK1;
end
`CHK1: begin
next_state = `CHK0;
end
`CHK0: begin
next_state = `ENABLE;
end
`ENABLE: begin
if (Ein) next_state = `ENABLE;
else next_state = `START;
end
endcase
end
/* Output logic */
assign LdChkSum = state[7];
assign Op1 = state[6];
assign Op0 = state[5];
assign OE0 = state[4];
assign OE1 = state[3];
assign OE2 = state[2];
assign OE3 = state[1];
assign Eout = state[0];
endmodule
module P2S(Ein, D3, D2, D1, D0, S, Eout, OE3, OE2, OE1, OE0, OEChk, Clk, Reset, Go);
input Ein;
input D3;
input D2;
input D1;
input D0;
output S;
output Eout;
output OE3;
output OE2;
output OE1;
output OE0;
output OEChk;
input Clk;
input Reset;
input Go;
reg S;
reg Eout;
reg OE0, OE1, OE2, OE3, OEChk;
/* Internals */
reg [7:0] state;
reg [7:0] next_state;
reg [3:0] data;
reg [1:0] cnt;
assign data = {D3, D2, D1, D0};
/* State encoding {OE0, OE1, OE2, OE3, OEChk, Eout, cnt[1:0]} */
`define START 8'b00000000 /* wait for enable */
`define SEND3a 8'b00010111 /* send first nibble */
`define SEND3b 8'b00010110 /* send first nibble */
`define SEND3c 8'b00010101 /* send first nibble */
`define SEND3d 8'b00010100 /* send first nibble */
`define SEND2a 8'b00100111 /* send second nibble */
`define SEND2b 8'b00100110 /* send second nibble */
`define SEND2c 8'b00100101 /* send second nibble */
`define SEND2d 8'b00100100 /* send second nibble */
`define SEND1a 8'b01000111 /* send third nibble */
`define SEND1b 8'b01000110 /* send third nibble */
`define SEND1c 8'b01000101 /* send third nibble */
`define SEND1d 8'b01000100 /* send third nibble */
`define SEND0a 8'b10000111 /* send fourth nibble */
`define SEND0b 8'b10000110 /* send fourth nibble */
`define SEND0c 8'b10000101 /* send fourth nibble */
`define SEND0d 8'b10000100 /* send fourth nibble */
`define SENDChka 8'b00001111 /* send check sum */
`define SENDChkb 8'b00001110 /* send check sum */
`define SENDChkc 8'b00001101 /* send check sum */
`define SENDChkd 8'b00001100 /* send check sum */
`define WAIT 8'b00000011 /* wait state for sending to end */
/* State flip-flops with reset */
always @(posedge Clk) begin
if (Reset) state = `START;
else state = next_state;
end
/* Next state logic */
always @(Ein or Go or state) begin
case(state)
`START: if (Ein) next_state = `SEND3a; else next_state = `START;
`SEND3a: if (Go) next_state = `SEND3b; else next_state = `SEND3a;
`SEND3b: if (Go) next_state = `SEND3c; else next_state = `SEND3b;
`SEND3c: if (Go) next_state = `SEND3d; else next_state = `SEND3c;
`SEND3d: if (Go) next_state = `SEND2a; else next_state = `SEND3d;
`SEND2a: if (Go) next_state = `SEND2b; else next_state = `SEND2a;
`SEND2b: if (Go) next_state = `SEND2c; else next_state = `SEND2b;
`SEND2c: if (Go) next_state = `SEND2d; else next_state = `SEND2c;
`SEND2d: if (Go) next_state = `SEND1a; else next_state = `SEND2d;
`SEND1a: if (Go) next_state = `SEND1b; else next_state = `SEND1a;
`SEND1b: if (Go) next_state = `SEND1c; else next_state = `SEND1b;
`SEND1c: if (Go) next_state = `SEND1d; else next_state = `SEND1c;
`SEND1d: if (Go) next_state = `SEND0a; else next_state = `SEND1d;
`SEND0a: if (Go) next_state = `SEND0b; else next_state = `SEND0a;
`SEND0b: if (Go) next_state = `SEND0c; else next_state = `SEND0b;
`SEND0c: if (Go) next_state = `SEND0d; else next_state = `SEND0c;
`SEND0d: if (Go) next_state = `SENDChka; else next_state = `SEND0d;
`SENDChka: if (Go) next_state = `SENDChkb; else next_state = `SENDChka;
`SENDChkb: if (Go) next_state = `SENDChkc; else next_state = `SENDChkb;
`SENDChkc: if (Go) next_state = `SENDChkd; else next_state = `SENDChkc;
`SENDChkd: if (Go) next_state = `WAIT; else next_state = `SENDChkd;
`WAIT: if (Ein) next_state = `WAIT; else next_state = `START;
endcase
end
/* Output logic */
assign OE0 = state[7];
assign OE1 = state[6];
assign OE2 = state[5];
assign OE3 = state[4];
assign OEChk = state[3];
assign Eout = state[2];
assign cnt = state[1:0];
assign S = data[cnt];
endmodule
