There is no other LOAD.
Date: Thu, 27 Feb 1997 11:20:46 -0800 (PST)
From: Jason Aten <firstname.lastname@example.org>
Subject: Please clarify 370 hw 7 prob#3
Dear Dr. Somani,
Could you please clarify number 3 of hw7:
3.Design a 4-bit parallel shifter with 4 stages. Each stage has 4 bits and
the shifter shift left by 1 position, if a new 4 bits value, denoted by i3
i2 i1 i0, along with a signal "NEW" is supplied to the circuit. Otherwise,
the shifter holds the value. You may use a universal shift register like
TTL 74194 (see Page 333). Notice that a 4 bit parallel shifter is
equivalent to 4 1-bit shifters. You should be able to read all 16 bits in
parallel, denoted by s15 .. s0 where s0 is the least significant bit of
the least significant stage and s15 is the most significant bit of the
most significant stage. Demonstrate the operation of your shifter using
appropriate input, i3 .. i0, and NEW, and output, s15 .. s0, for your
synario implemenation. Submit the schematic and waveforms.
Specifically, when does the shifter load, hold, and shift?
In particular, I assume that the load signal causes the 4-bit word to be
loaded into the right most (lease significant) 4 flip-flops, overwriting
the current values. Please correct me if I misinterpert.
However, I am confused about the phrase "Otherwise, the shifter holds the
value" which sounds like the shifter does not shift unless given an
explicit SHIFT ENABLE signal.
I would tend to think that the shifter would shift on clock edges as a
default. The only way to not shift is to be in LOAD mode, in which case
bit 3 still shifts to bit 4, but bits 0-3 are replaced by i3..i0 after the
clock edge. Is this correct?
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