I would not recommend using four different clocks since that
reduces designing a clock to simply an interface design and that is
not the point of the exercise.
I would recommend the following approach - Note that each of the
counters is proceeding from 0 upto some other value. e.g if we call the
counters respectively H1,H0,M1,M0 (for hour and minute), with 1 denoting
the more significant digit,
M0 goes from 0 to 9
M1 goes from 0 to 5
H0 goes from 0 to 9 when H1 is 1 or 0
H0 goes from 0 to 3 when H1 is 2
H1 goes from 0 to 2
Thus, all you have to do is let the four BCD counters count and have the
clock to them be supplied each time a less significant register has
reached a specific number of values. So, M1 receives a clock only when M0
reaches 9 (or 0 depending on your design). Some such logic can be derived
for the clock of each of the four counters. All that remains is to figure
out the condition under which the register does something besides simple
up-counting, which in our case means going back to 0. Just derive the
conditions for going back to 0 for each register and feed that to the
clear input. Of course, as in any design problem, there are other ways to
do it without using a clear, so dont worry. If your ckt is functional, you
have used some structure to build it and that is fine.
NOTE about the hour counters: Since we are doing everything in BCD,
getting the clear functions right for the hour counters is slightly more
challenging i.e. they DONT simply clear each time the next lower counter
has finished one full cycle. The minute counters do that, of course.
Himanshu
http://www.cs.washington.edu/homes/nautiyal