> We have a question about the "Clock Display" module on the data path
> diagram you provided. We can see that the two inputs to the mux are the
> normal clock and the output from the 4-bit parallel shift register. We
> are a little confused about the origin of the "SD" input. Is the purpose
> of this mux to display any new input (for any non-clock mode), as opposed
> to the normal clock readout? Thanks for the help.