# WRITING A VERILOG TEST FIXTURE (USING BUSES)

#### WHAT IS A BUS (AND WHY IS IT USED)?

Buses inVerilog serve the same purpose as do aliases in ABEL: they abstract you out of binary by letting you make assignments in the "normal" base-10 decimal system your mind "naturally" thinks in. Why is this a good thing? For the same reason abstraction is good: it lets you think about the design you are working on at a high level without being distracted by the details of implementation. Instead of trying to figure out what "37" is in binary, you just say "37" and you are done. You could, of course, take the time yourself to compute "37"'s binary equivalent, but why bother with the extra work when the computer will do it for you?

#### HOW TO USE BUSES

The following example shows very simply everthing you need to know to use buses in Verilog. We have created a bus named "X" which is comprised of the inputs "X3,X2,X1,X0", and then assigned it the arbitrary value "2".

To create "X" we used the following syntax:

`define X {X3,X2,X1,X0}

Please note that the character before the define is not an apostraphe, but the " ` " character on the tilda key. Note also that our bits are listed from high to low and that you do not need to use a semicolon to end the line.

To assign "X" an arbitrary value, we used the following syntax:

`X = 2;

Note once again that the character preceeding the "X" is not an apostraphe and that here you do need a semicolon to end the line. This decimal assignment is equivalent to the four binary assignments:

X3 = 0;
X2 = 0;
X1 = 1;
X0 = 0;