//--------------------------------------------------------------------------------------------------
//
// Title       : phase2_tf
// Design      : mips
// Author      : Steven
// Company     : UW CSE
//
//-------------------------------------------------------------------------------------------------
//
// File        : phase2_tf.v
// Generated   : Thu Aug 31 14:16:33 2006
// From        : lab1_phase2_partc_TB_settings.txt
// By          : tb_verilog.pl ver. ver 1.2s
//
//-------------------------------------------------------------------------------------------------
//
// Description : 
//
//-------------------------------------------------------------------------------------------------

`timescale 1ps / 1ps
module phase2_tf;


//Internal signals declarations:
reg CLK;
reg WriteToRD;
wire Zilch_actual;
reg Zilch;
reg [1:0]ALUOp;
wire [31:0]ALUOut_actual;
reg [31:0]ALUOut;
reg RegWrite;
reg SrcASel;
reg SrcBSel;
reg [1:0]ExtOp;
reg [31:0]Inst;
wire Overflow_actual;
reg Overflow;
//LOG file declaration.
integer report_file;

//Wait time declaration used in ports monitoring.
//One parameter is declared for every port.
parameter Default_wait_time = 10;
parameter Zilch_WaitTime = Default_wait_time;//WaitTime Parameter for port Zilch
parameter ALUOut_WaitTime = Default_wait_time;//WaitTime Parameter for port ALUOut
parameter Overflow_WaitTime = Default_wait_time;//WaitTime Parameter for port Overflow

//Simulation time
parameter SimulationTime = 64'd1000000 + Default_wait_time + 1;

//Errors counter
integer errors_counter;

//Block of Comparison functions declarations. A separate function for each output port is defined.
//Comparison function for port "Zilch"
function compare_Zilch;
input  UUT_output;
input  PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_Zilch = 1'b1;
		else compare_Zilch = 1'b0;
	end
endfunction
//Comparison function for port "ALUOut"
function compare_ALUOut;
input [31:0] UUT_output;
input [31:0] PATTERN;
	begin
		if (UUT_output !== PATTERN) compare_ALUOut = 1'b1;
		else compare_ALUOut = 1'b0;
	end
endfunction

// Unit Under Test port map
	Datapath UUT (
		.CLK(CLK),
		.WriteToRD(WriteToRD),
		.Zilch(Zilch_actual),
		.ALUOp(ALUOp),
		.ALUOut(ALUOut_actual),
		.RegWrite(RegWrite),
		.SrcASel(SrcASel),
		.SrcBSel(SrcBSel),
		.ExtOp(ExtOp),
		.Inst(Inst),
		.Overflow(Overflow_actual));

initial
	begin
		report_file=$fopen("$DSN\\src\\Tests\\phase2_report.log");
		errors_counter = 0;
		#SimulationTime;
		if (errors_counter)
		begin
			$display("Errors were encountered, differences are listed in phase2_report.log");
			$fdisplay(report_file,"Some vectors failed.");
		end
		else
		begin
			$display("All vectors passed.");
			$fdisplay(report_file,"All vectors passed.");
		end
		$fclose(report_file);
		$finish;
	end
//Below code was generated based on waveform file: "e:\my_designs\NewLabs\mips378\mips378\mips\compile\phase2.vhr"

initial
begin : STIMUL // begin of stimulus process
	#0
	CLK = 1'b0;
	ExtOp = 2'b01;
	SrcASel = 1'b0;
	Inst = 32'b00100000100010000000000000000101;
	ALUOp = 2'b11;
	Zilch = 1'b0;
	RegWrite = 1'b1;
	WriteToRD = 1'b0;
	ALUOut = 32'b00000000000000000000000000001001;
	SrcBSel = 1'b1;
    #310000; //100
	CLK = 1'b1;
    #20000; //310000
	CLK = 1'b0;
    #20000; //330000
	CLK = 1'b1;
    #100; //350000
	Inst = 32'b00100000100010011111111111111011;
	ALUOut = 32'b11111111111111111111111111111111;
    #19900; //350100
	CLK = 1'b0;
    #20000; //370000
	CLK = 1'b1;
    #100; //390000
	Inst = 32'b00100100100010100000000000000101;
	ALUOut = 32'b00000000000000000000000000001001;
    #19900; //390100
	CLK = 1'b0;
    #20000; //410000
	CLK = 1'b1;
    #100; //430000
	Inst = 32'b00100100100010111111111111111011;
	ALUOut = 32'b11111111111111111111111111111111;
    #19900; //430100
	CLK = 1'b0;
    #20000; //450000
	CLK = 1'b1;
    #100; //470000
	Inst = 32'b00101000100011001111111111111111;
	Zilch = 1'b1;
	ALUOut = 32'b00000000000000000000000000000000;
    #19900; //470100
	CLK = 1'b0;
    #20000; //490000
	CLK = 1'b1;
    #100; //510000
	Inst = 32'b00101100100011011111111111111111;
	Zilch = 1'b0;
	ALUOut = 32'b00000000000000000000000000000001;
    #19900; //510100
	CLK = 1'b0;
    #20000; //530000
	CLK = 1'b1;
    #100; //550000
	ExtOp = 2'b00;
	Inst = 32'b00110000101011100000000000001011;
    #19900; //550100
	CLK = 1'b0;
    #20000; //570000
	CLK = 1'b1;
    #100; //590000
	Inst = 32'b00110100101011110000000000001011;
	ALUOut = 32'b00000000000000000000000000001111;
    #19900; //590100
	CLK = 1'b0;
    #20000; //610000
	CLK = 1'b1;
    #100; //630000
	Inst = 32'b00111000101110000000000000000110;
	ALUOut = 32'b00000000000000000000000000000011;
    #19900; //630100
	CLK = 1'b0;
    #20000; //650000
	CLK = 1'b1;
    #100; //670000
	ExtOp = 2'b11;
	SrcASel = 1'b1;
	Inst = 32'b00000000000010111100100010000010;
	ALUOp = 2'b10;
	WriteToRD = 1'b1;
	ALUOut = 32'b00111111111111111111111111111111;
	SrcBSel = 1'b0;
    #19900; //670100
	CLK = 1'b0;
    #20000; //690000
	CLK = 1'b1;
    #100; //710000
	Inst = 32'b00000000000011111000011101000000;
	ALUOut = 32'b11100000000000000000000000000000;
    #19900; //710100
	CLK = 1'b0;
    #20000; //730000
	CLK = 1'b1;
    #100; //750000
	Inst = 32'b00000000000100001000100101000011;
	ALUOut = 32'b11111111000000000000000000000000;
    #19900; //750100
	CLK = 1'b0;
    #20000; //770000
	CLK = 1'b1;
    #100; //790000
	ExtOp = 2'b00;
	SrcASel = 1'b0;
	Inst = 32'b00000000010010111001000000000110;
	ALUOut = 32'b00111111111111111111111111111111;
    #19900; //790100
	CLK = 1'b0;
    #20000; //810000
	CLK = 1'b1;
    #100; //830000
	Inst = 32'b00000011101011111001100000000100;
	ALUOut = 32'b11100000000000000000000000000000;
    #19900; //830100
	CLK = 1'b0;
    #20000; //850000
	CLK = 1'b1;
    #100; //870000
	Inst = 32'b00000000101100111010000000000111;
	ALUOut = 32'b11111111000000000000000000000000;
    #19900; //870100
	CLK = 1'b0;
    #20000; //890000
	CLK = 1'b1;
    #100; //910000
	ExtOp = 2'bXX;
	SrcASel = 1'bx;
	Inst = 32'bXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX;
	ALUOp = 2'bXX;
	Zilch = 1'b1;
	RegWrite = 1'bx;
	WriteToRD = 1'bx;
	ALUOut = 32'b00000000000000000000000000000000;
	SrcBSel = 1'bx;
    #19900; //910100
	CLK = 1'b0;
    #20000; //930000
	CLK = 1'b1;
    #20000; //950000
	CLK = 1'b0;
    #20000; //970000
	CLK = 1'b1;
    #10000; //990000
end // end of stimulus process
	



//Set of always bloks for ports monitoring.
//One block per output port.
//Always block for monitoring port "Zilch";
always @(Zilch or Zilch_actual)
	begin
		#Zilch_WaitTime
		if (compare_Zilch(Zilch,Zilch_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port Zilch: Expected value is %b, Actual value is %b",Zilch,Zilch_actual);
			$display($realtime,,"ps; Error on port Zilch: Expected value is %b, Actual value is %b",Zilch,Zilch_actual);
		end
	end
//Always block for monitoring port "ALUOut";
always @(ALUOut or ALUOut_actual)
	begin
		#ALUOut_WaitTime
		if (compare_ALUOut(ALUOut,ALUOut_actual))
		begin
			errors_counter = errors_counter + 1;
			$fdisplay(report_file,$realtime,,"ps; Port ALUOut: Expected value is %b, Actual value is %b",ALUOut,ALUOut_actual);
			$display($realtime,,"ps; Error on port ALUOut: Expected value is %b, Actual value is %b",ALUOut,ALUOut_actual);
		end
	end

endmodule