CSE 378 Fall 2006

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CSE 378 Fall 2006

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CSE 378 Component Library We built a set of verilog components that are useful for constructing your MIPS processor. Get the library here.  This link points to an archived Active-HDL design named lib378. You should restore this into an Active-HDL workspace.  To install the library, unzip the file to a convenient location. Then, in ActiveHDL, do the following: Go to File->Open, and browse to the directory where you unzipped the library. open the file named lib378.adf You should now have a design called "lib378" Make the lib378 design active using Right-Click->Set as Active Design Right-Click on the file "update_lib378.do" and select Execute This is a macro that cleans out the library, recompiles the files, and restores the read-only status of the library. After you complete this portion, the library lib378.lib has been updated from the included source files. Now open the Libraries window, right click and select "Attach Library...", and select the .lib file in the newly created lib378 folder. Once this is done, right click on the library, and select "Add to Symbols Toolbox", then right click again, and select "Make Global". Registers:   Component Description register Basic register with initial value register_r Register w/ reset signal register_re register_r w/ clock enable (Load Signal) register_file Standard 32 bit register file with 32 registers registerfile2 32 bit register file with 32 registers and writethrough capability. DO NOT USE WITH LAB 1   Multiplexors:   Component Description mVw_2_1_top/mVw_2_1_bot Arbitrary width 2:1 multiplexor mVw_4_1_top/mVw_4_1_bot Arbitrary width 4:1 multiplexor m32w_2_1_top/m32w_2_1_bot 32-bit width 2:1 multiplexor m32w_4_1_top/m32w_4_1_bot 32-bit width 4:1 multiplexor m6w_2_1 6-bit width 2:1 multiplexor m5w_2_1 5-bit width 2:1 multiplexor dm32w_1_4_top/dm32w_1_4_bot 32-bit width 1:4 demultiplexor   Arithmetic Units:   Component Description adder arbitrary width 2 input adder MIPSALU MIPS ALU   Wire Units:   Component Description extender Extender unit that performs left alignment, sign and zero extension, and shamt extraction Memories:   Component Description BIOSROM256x32 instruction memory Ram256x32_sw_ar_wb 256 word memory, supports write byte, half-word, and word.  USE FOR LAB1 Memory_Toplevel Top level memory system for pipelined processors CacheMemorySystem_4Word Top level memory system for pipelined processors with 4 word line caches Caches:   Component Description ICache_4Word Instruction cache with 4 word cache lines ICache_1Word Instruction cache with 1 word cache lines Misc:   Component Description ClockSystem clock and local reset generator constant represent a constant Control:   Component Description ALUControl controller for MIPSALU IO Devices:   Component Description SerialUART Serial I/O Device MemoryMappedIO Controls the LEDs and reports on button statuses VGA_Output VGA I/O Device

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