Behavioral representation

• Specified using HDLs (e.g. Verilog or VHDL)

• Hierarchy

  • Algorithmic description
  • Functional description
    • Example: Adder carry (includes timing)
  • Boolean equations
  • Behavioral specification

module carry (co, a,b,c);
output co;

input a,b,c;
wire #10 co=(a&b)|(a&c)|(b&c)

endmodule

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