Class
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Topic
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Reading
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Milestones
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Dynamic Branch Prediction 4/2, 4/7
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Review of pipelining
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SimpleScalar homework due April 7
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Dynamic branch prediction
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Sections 2.3 and 2.9; pp. 121-127
SimpleScalar documentation, project report guidelines,
and sample project report (available in Homework section)
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Predicated execution
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Appendix G.4
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Execution Cores 4/9, 4/14, 4/16
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Superscalars and static scheduling
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|
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Overview of dynamic scheduling
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Section 2.4 to p.92, Section 2.8
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Tomasulo's algorithm
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Section 2.4 p.92 to its end,
Section 2.5
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R10000-style dynamic scheduling (a physical register pool)
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The Smith/Sohi article for superscalars in a nutshell.
In the R10000 article read from register mapping,
p. 32, through Register files, p. 35.
|
VLIW Processors 4/21
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Software techniques to exploit ILP
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Section G.3 covers compiler techniques that we will discuss briefly.
|
Branch prediction homework due April 21
|
VLIW machines
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Section 2.7 and G.6 through p.G-40
It's not necessary to know all the details of this architecture.
Let the lecture be your guide.
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Initial project discussion with project groups: April 21, 1:30 to 3:30, my office.
Sign up for a 15 minute slot.
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Memory Hierarchy 4/23
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Advanced caching techniques
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Section 5.2
|
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Midterm 1 4/28
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Exam is in class, 1.5 hours
|
|
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Multiprocessors 4/30, 5/5, 5/7
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Overview of multiprocessing
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Section 4.1
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Two-pager describing your project plans due Thursday, April 30.
|
Cache coherence, snooping, and directory protocols
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Section 4.2,
Section 4.4
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Synchronization
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Section 4.5
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First project milestone due Thursday, May 14.
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Current multi-core topic
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Read a current research paper
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Multithreading 5/12, 5/14
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Tera-style multithreading
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Read the Tera paper (PDF).
|
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Simultaneous multithreading
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Section 3.5 and the SMT paper
|
Dataflow Computers 5/19, 5/21
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Dataflow Machines
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After reading them over, I don't think any of the papers on the
early dataflow machines are appropriate for classroom use. There
are no general overview papers. So just listen to the lecture.
|
|
Wavescalar architecture and implementation
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The WaveScalar Architecture and
An overview of the WaveScalar implementation.
|
No Formal Lecture 5/26, 5/28
|
Project meetings instead.
Vince will administer course evaluations.
|
|
Second project milestone due Thursday, May 28.
|
Guest Lecturers 6/2
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Joe Devietti, CSE Grad Student
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Deterministic Shared Memory Multiprocessors
|
|
Georg Seelig, Assistant Professor, EE & CSE
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Molecular Logic Circuits
|
======================================================== -->
Project Reports 6/4
|
|
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Final report due Thursday, June 4, at midnight.
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Midterm 2 6/8, 10:30
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EEB 042
|