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 CSE 471: Computer Design and Organization - Spring 2010
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CSE 471 Schedule (Spring 2010)

This course schedule will be updated, so check it often.
The dates for the readings indicate the day that the reading should have been read.

 
Class
Topic
Reading
Milestones
Dynamic Branch Prediction
3/30, 4/1
Review of pipelining
Dynamic branch prediction Sections 2.3 and 2.9; pp. 121-127
SimpleScalar documentation, project report guidelines,
and sample project report (available in Homework section)
Predicated execution Appendix G.4
Execution Cores
4/6, 4/8, 4/13
Superscalars and static scheduling SimpleScalar homework due Tuesday, April 6
Overview of dynamic scheduling Section 2.4 to p.92,
Section 2.8
Tomasulo's algorithm Section 2.4 p.92 to its end,
Section 2.5
R10000-style dynamic scheduling (a physical register pool) The Smith/Sohi article for superscalars in a nutshell.
In the R10000 article read from register mapping, p. 32, through Register files, p. 35.
VLIW Processors
4/15, 4/20
Software techniques to exploit ILP Section G.3 covers compiler techniques that we will discuss briefly. Branch prediction homework due Thursday, April 15
VLIW machines Section 2.7 and G.6 through p.G-40
It's not necessary to know all the details of this architecture. Let the lecture be your guide.
Memory Hierarchy
4/20
Advanced caching techniques Section 5.2
Preparing for the Midterm
4/22
Discuss the midterm and cover any outstanding material. Cache homework milestone due Thursday, April 22.
Midterm 1
4/27
Exam is in EE042, 1.5 hours
Multiprocessors
4/29, 5/4, 5/6
Overview of multiprocessing Section 4.1 Cache homework due Thursday, April 29.
Cache coherence, snooping, and directory protocols Section 4.2,
Section 4.4
Synchronization Section 4.5
Joe Devietti, CSE Grad Student This paper, "DMP: Deterministic Shared-Memory Multiprocessing", International Conference on Architectural Support for Programming Languages & Operating Systems, 2009, is just FYI. You're not responsible for reading it. First coherency milestone, Thursday, May 6.
Multithreading
5/11, 5/13
Tera-style multithreading Lightly skim the Tera paper (PDF).
Simultaneous multithreading Section 3.5 and the SMT paper
Dataflow Computers
5/18, 5/20
Dataflow Machines After reading them over, I don't think any of the papers on the early dataflow machines are appropriate for classroom use. There are no general overview papers. So just listen to the lecture.
Wavescalar architecture and implementation Skim The WaveScalar Architecture and An overview of the WaveScalar implementation. Use this to reinforce what we discuss in lecture; don't pay much attention to any new material covered in these papers.
Prepare for the second midterm.
5/25
Any material not yet covered.
The Wave of the Future
5/27
Andrew Putnam, Microsoft Research, formerly a CSE Grad Student This paper, "Performance and Power of Cache-Based Reconfigurable Computing", International Symposium of Computer Architecture, 2009, is just FYI. You're not responsible for reading it. Second coherency milestone, Thursday, May 27.
Georg Seelig, Assistant Professor, EE & CSE Molecular Logic Circuits
Midterm 2
6/1, 10:30
Exam is in CSE 403, 2 hours Final homework report due Thursday, June 3, at midnight.


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