CSE as AND gate University of Washington Department of Computer Science & Engineering
 CSE 567 - Principles of Digital Systems Design
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Lecture Notes
 1 Review of Combinational Logic
 2 Regular Logic Structures
 3 Verilog
 4 Registers
 5 Finite State Machiness
 6 More Verilog
 7 FPGA Architectures
Assignments
 Homework #1
 Solution #1CSE only
 Homework #2
 Solution #2
 Homework #3
 Solution #3
 Project #1
 Project #2
 Homework #4
 Solution #4
 Homework #5
 Solution #5
Project Information
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 Project Overview
 Design Tools
 Getting Started with Sue
Tutorials
 SUE Introduction
 SUE Intermediate
 Verilog
 Virtex
   
Time: TTh 9:00-10:20
Place: EE1 045
Office Hours Phone
Instructor: Carl Ebeling, ebeling@cs, M 2:30-3:30/ W 1:30-2:30 Sieg 215, 543-9342
TA: Charles Gordon, cgordon@cs, Drop in Sieg 431, 543-5143

Hypermail archive of all mail sent to cse567@cs. (You must subscribe to the mailing list. )
Please use the cse567 email liberally to ask questions and share information with each other.

Course Goals: To provide in-depth understanding of digital systems and their design, including specification, synthesis, and implementation.

Catalog Description: (3 credits) Principles of logic design, combinational and sequential circuits, minimization techniques, structured design methods, CMOS technology, complementary and ratioed gates, delay estimation and performance analysis, arithmetic circuits, memories, clocking methodologies, synthesis and simulation tools, VLSI processor architecture, application-specific computation.

Prerequisites: An introductory digital design class or equivalent. A working knowledge of combinational and sequential logic.
Familiarity with the department's computing environment: Unix/Windows NT

Grading: Homeworks, Project, Midterm, Final Exam approximately 20%, 40%, 15%, 25%, resp. There will be weekly homework assignments, concentrated mostly in the first 2/3 of the class. The latter part of the class will focus on the design of a substantial project, which involves designing and testing hardware to implement an interesting system like a video camera or network monitor. The quizzes and final exam are open book.

Late Policy: Turnins due by 5:00PM on due date. 20% off for one day late (Monday, for Friday due dates). See instructor if you slip even more.


Portions of the CSE 567 Web may be reprinted or adapted for academic nonprofit purposes, providing the source is accurately quoted and duly credited. The CSE 567 Web: © 1993-2001, Department of Computer Science and Engineering, University of Washington.


CSE logo Department of Computer Science & Engineering
University of Washington
Box 352350
Seattle, WA  98195-2350
(206) 543-1695 voice, (206) 543-2969 FAX
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