Multi-Level Optimization

• 1. Reduce number of literals

  • fewer literals means less transistors (less space)
  • fewer inputs implies faster gates (less switches in series)
  • fan-ins (# of gate inputs) are limited in some technologies

• 2. Reduce number of gates

  • number of gates (or gate packages) influences manufacturing costs

• 3. Reduce number of levels of gates

  • fewer levels of gates implies reduced signal propagation delays
  • minimum delay configuration typically requires more gates (wider less deep circuits)

• Explore tradeoffs between increased circuit delay and reduced gate count

  • automated tools to optimize logic and explore possibilities

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