Random Logic Implementation

Table of Contents

Random Logic Implementation

Regular Two-Level Logic

Complete Minterm Array

Memory Example

Memory Alternatives

Programmable Logic Array

PLAs

PLA Example

Another PLA Example

PLA Example

Programmable Array Logic (MMI PAL)

PALs

PALs vs. Discrete Logic

Limits of PALs

Regular Structure forTwo-Level Combinational Logic

Multiplexer Logic

Multiplexer Logic (cont’d)

Multiplexer Logic (cont’d)

Multiplexers (cont’d)

Decoder Logic

Decoders/Demultiplexers (cont’d)

Decoders/Demultiplexers (cont’d)

Timing Behavior of Circuits

Timing Comparison ofAlternative Implementations

Combinational Hazards

Kinds of Hazards

Hazards

Static Hazards

Hazard-Free Circuit

Detecting/Removing Static Hazards

Hazard-Free Logic

What About PLAs, PALs and ROMs?

Dynamic Hazards

Dynamic Hazard Example

Time Response in Combinational Networks

Case Study: N-bit Adder

Half Adder

Full Adder

Full Adder (cont'd)

Full and Half Adders

Adder/Subtractor

Ripple-Carry Adders

Ripple-Carry Adders (cont'd)

Carry-Lookahead Adders

Carry-Lookahead Adders (cont'd)

Carry-Lookahead and Parallel-Prefix

Carry-Lookahead Implementation

Carry-Lookahead Implementation (cont’d)

Carry-Lookahead Implementation (cont’d)

Carry-Lookahead Adder

Carry-Select Adder

Carry-Select Adder (cont’d)

Carry-Select Adder (cont'd)

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