Table of Contents
CAD for FPGAs
Technology Mapping for Gates
Technology Mapping for FPGAs
Technology Mapping for LUT-based FPGAs
Technology Mapping by First-Fit Bin-Packing
Decomposition
Fanout and Reconvergent Paths
Duplication of Logic
Placement and Routing
Placement
Approaches to Placement (Analytical)
Approaches to Placement (Probabilistic)
Placement Using Simulated Annealing
Probabilistic Hill-Climbing
Placement Using Simulated Annealing (cont’d)
Routing
Routing (cont’d)
First-Order Congestion
1st Order Congestion Resolution
2nd Order Congestion
2nd Order Congestion Resolution
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Author: LIS
Email: 567-webmaster@cs.washington.edu
Home Page: http://www.cs.washington.edu//education/courses/567/CurrentQtr
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