CSE 567: Principles of Digital Systems Design

Carl Ebeling, Fall 1999

Welcome to the 567 Home Page


Staying in touch:

E-mail Archive: All messages sent to the class (cse567@cs.washington.edu). [Last update:10/07/99 at 11PM.]
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Course Information

Staff:


Accounts and access to Sieg 424 Lab

For this course, you will need an NT account (CSEPCLAB domain) and access to the 424 HW Lab, where the hardware setup will be located. If you do not have an NT workstation where you can run the Xilinx tools, you will also need access to the 329 PC NT Lab.

If you are a CSE graduate student, then you already have an NT account and access to 424. If you are not, then you will have to apply for an account and a key to 424. Please go to this page for directions on how to do this.


Lecture notes

  1. Overview
  2. Combinational Logic: Introduction
  3. Combinational Logic: Two-Level Minimization
  4. Combinational Logic: Regular Structures
  5. Introduction to Sequential Logic
  6. Finite State Machines
  7. Verilog
  8. Introduction to FPGAs
  9. Multi-Level Logic Synthesis
  10. Pipelining and Retiming

Homework Assignments

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