CSE 590g, Architecture Lunch
CSE 590g - Architecture Lunch
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Course organizer:
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Jean-Loup
Baer
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Meeting time:
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Tuesdays, 12:30pm to 1:20pm, in Sieg 227
CSE590G, aka "architecture lunch", will continue this quarter with
the same format as previous years,
i.e., selection of papers to be discussed
at the beginning of the quarter, distribution on week n of
the paper to
be read during the week and discussed at week (n+1). There might be
be a few formal presentations of work in progress by
esteemed members of the "lunch" and mostly (hopefully heated) discussions
on papers from the literature.
Schedule for Winter Quarter 1997
- 1/14: "Performance comparison of ILP machines with cycle time evaluation"
Hara et al., ISCA96, pp. 213 ff. presented by Peter van Vliet
- 1/21: "Early experience with message-passing on the SHRIMP multicomputer"
by Felten et al. ISCA96, pp. 296 ff. presented by Geoff Voelker
- 1/28: "Correlation and aliasing in dynamic branch predictors" by
Selchrest et al. ISCA96, pp. 22 ff. presented by Ori Gershony
- 2/4: No class
- 2/11: "Informing memory operations: providing memory performance feedback in modern processors"
by Horowitz et al. ISCA96, pp. 260 ff. presented by E Lewis
- 2/18: "Register file design considerations in dynamically scheduled processors"
by Farkas et al. HPCA-96, pp. 40 ff. presented by Wayne Wong
- 2/25: "Synchronization and Communication in the T3E Multiprocessor"
by Scott ASPLOS-VII 1996, pp. 26 ff. presented by Jason Secosky
- 3/4: "Performance study of a multithreaded superscalar microprocessor"
by Gulati et al., HPCA-96, pp. 291 ff. presented by Jack Lo
- 3/11: "The intrinsic bandwidth requirements of ordinary programs"
by Huang and Shen ASPLOS-VII, 1996 pp. 105 ff. presented by Dave Grove
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