| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| lcm_config|u0 |
19 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| lcm_config |
2 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| ccd_config|u0 |
35 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| ccd_config |
6 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| display |
27 |
2 |
0 |
2 |
15 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|wrfull_eq_comp |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|rdempty_eq_comp |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe12 |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|ws_dgrp |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|wraclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe7 |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|rs_dgwp |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|fifo_ram|output_mux |
195 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|fifo_ram|address_decoder |
4 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|fifo_ram |
34 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo|dcfifo_component|auto_generated |
29 |
0 |
0 |
0 |
26 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo|fifo |
29 |
0 |
0 |
0 |
26 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync|outfifo |
29 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| outputAsync |
31 |
0 |
0 |
0 |
26 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| fb|memory |
57 |
0 |
1 |
0 |
36 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
| fb|dpc |
20 |
0 |
0 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| fb |
40 |
0 |
0 |
0 |
46 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|wrfull_eq_comp |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|rdempty_eq_comp |
8 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|ws_dgrp|dffpipe9 |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|ws_dgrp |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|rs_dgwp|dffpipe6 |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|rs_dgwp |
6 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|rdaclr |
3 |
1 |
0 |
1 |
1 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|fifo_ram|output_mux |
267 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|fifo_ram|address_decoder |
4 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|fifo_ram |
43 |
0 |
0 |
0 |
33 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|wrptr_gp |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|wrptr_g1p |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated|rdptr_g1p |
3 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo|dcfifo_component|auto_generated |
38 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo|fifo |
38 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync|infifo |
38 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| inputAsync |
41 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| filter_inst|row |
28 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| filter_inst |
45 |
0 |
1 |
0 |
42 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| u5 |
3 |
28 |
3 |
28 |
28 |
28 |
28 |
28 |
0 |
0 |
0 |
0 |
0 |
| b |
33 |
0 |
4 |
0 |
42 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| icamera |
18 |
8 |
0 |
8 |
46 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
| p0 |
1 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| p50 |
1 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| rd |
2 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |