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My research interests bridge the gap between computer science and electrical engineering.
Some favorite topics are computer architecture, reconfigurable computing, high-performance
computing, and networks.
Current Research My current research runs along the theme of using dataflow architectures. The von Neumann computer architectures are no longer providing the exponential performance increases for applications alone, so architectures must evolve to continue accelerating applications.However, software engineers don't have great motivation to change their programming model. The sequential con Neumann model has proven to be an effective, efficient way to program. If architects simply provide parallel hardware with a totally different programming model, then software engineers will have a sharp learning curve to adopt the new architectures. Whether software developers are willing to change their programming model, practices, and tools for improved performance is uncertain. I seek to find ways to harness the power of parallel architectures with as little change to the existing programming model as possible. I focus on dataflow architectures, which are a promising way to run sequential code on a parallel architecture. I am particularly interested in what the memory model for hybrid dataflow/von Neumann systems should look like, what the programming model should look like, and how to implement the dataflow hardware to ensure high-performance on sequential code. Here are some of the projects that I am currently working on: WaveScalar WaveScalar is a dataflow architecture that offers solutions to some of the most troubling problems facing computer architects: reliability, scalability, complexity, power, and performance. It is a dataflow architecture that is the first to support imperative languages, such as C/C++ and Java.WaveScalar is a tiled architecture, which means that a simple tile is replicated many times to form the processor. In WaveScalar, this tile is known as a Processing Element (PE). These PEs are organized hierarchically. Two PEs combine to form a Pod. Four Pods form a Domain. Four domains form a Cluster. And Clusters are replicated to make larger and larger WaveScalar processors. With only one undergraduate assistant (Ken Michaelson), I designed and implemented numerous RTL models of WaveScalar using 90nm ASIC technology libraries. The final model had an aggressive clock cycle of 22 FO4, occupied a reasonable die area (42.5 mm2 per tile), and used only 85 watts. The research showed that a WaveScalar processor can be implemented within realistic silicon die size and power constraints. Research also showed how to tune architectural parameters to minimize the clock cycle and the area. My next step is to look into WaveScalar as a platform for reconfigurable computing. This is essentially making WaveScalar a "soft" processor implemented on a reconfigurable fabric (like an FPGA). Compared to an ASIC implementation of a processor, FPGAs typically require 10-20x the area, use 10x the dynamic power, and run at 3-4x lower frequency. So to make up the difference, FPGAs need to use take advantage of the fact that the hardware can adapt to better match the application.
CHiMPS CHiMPS is a project that aims to compile high-level language (HLL) code (such as C/C++) to custom hardware for FPGAs. The goal is to accelerate supercomputing applications in ways that standard von Neumann processors simply can't. But CHiMPS is much more than another C-to-Gates compiler.CHiMPS provides an ISA for HLLs to target FPGAs. This ISA looks similar to a standard RISC processor, with some important additions. It is a static dataflow architecture (recognize a theme to my research here? :-), which allows the architecture to eliminate artificial control flow constraints. It also enables parallelism through pipelining. My role on the project is as the hardware implementation research engineer. I am focused on the memory model, which is a critical piece of the implementation. FPGAs have hundreds of small memories distributed throughout the chip. This allows orders-of-magnitude more memory accesses per cycle than a traditional monolithic cache, but using these memories effectively and maintaining coherence are very difficult challenges. RAMP RAMP, which stands for Research Accelerator for Multiple Processors, is a project that involves a number of top universities, including the University of Washington. The goal is to make a usable, interactive hardware platform with 1000 processor cores that developers can use to test out software on a possible future architecture. This will also serve as a platform for computer architecture researchers to share their designs, allowing a unprecidented capability to adapt and verify designs from across the world instantly.My primary responsibilities on RAMP are as the graduate student coordinator, and as the author and maintainer of the network switch. I am organizing the first RAMP bootcamp, which aims to get the RAMP graduate student community together to talk about RAMP, and to lay the foundation for building a full RAMP system. The bootcamp is organized and run exclusively by graduate students, and we hope to develop RDL implementation of a LEON-3 based multiprocessor system. Undergraduate Research I had the opportunity to do some very interesting research while I was an undergraduate. I firmly believe that I did more valuable and more interesting research at the University of San Diego than I could have at any large research institution. This is in large part due to Dr. Daniel Sheehan, who gave me a world of opportunities, and to whom I am extremely grateful.MEMS Oscillator Along with Dr. Daniel Sheehan and Dr. Jeff Wright working on a project that involves novel ways of using the electric field in the P-N junction of a semiconductor to make a motor/generator. There are several variations ofthe device, including the piston and the hammer-anvil. The device has interesting connotations for the 2nd Law of Thermodynamics.Dr. Daniel Sheehan is in the Department of Physics at the University of San Diego Dr. Jeff Wright is in the Department of Mathematics and Computer Science at the University of San Diego Zero Gravity Fluid Dynamics One of the best research experiences of my life was my fluid dynamics research conducted under the NASA Reduced Gravity Student Flight Opportunity Program (RGSFOP). The program allows undergraduate researchers to perform experiments in zero gravity aboard the NASA KC-135 "Weightless Wonder" (more commonly known as the "Vomit Comet"). In 2001-2002, I lead a team of five undergraduates in an investigation of Faraday waves in microgravity. From 2002-2003, I lead a team of five undergraduates and one one high school student in an investigation of capillary action in microgravity. For more info on the zero gravity research, visit my zero gravity page at http://www.sandiego.edu/zerogravity.
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