This is a collection of various little thoughts and observations I've had.

• Time interleaving a matrix multiply

The following notes are from the CMU days, listed in chronological order (oldest first):

• "Small" feedback in queue based architectures
  Associated images:
  1. approach 1
  2. approach 2
  3. pitfall 1
  4. pitfall 2
  5. approaches 3, 4, and 5
• Operation widths in queue based architectures
  Associated images:
  1. Carry through the queue
  2. Carry through extra, implicit, register
  3. Carry through multiple queues
  4. Carry through implicit register and multiple queues
  5. Family of operations
• HCU complications due to multiple queues
  Associated image
• A detailed look at implementing delays with the feedback queue
  Associated image
• A new relaxation of the queue architecture
• An analysis of the circuitry for operand queues
• All about feedback
• HASTE Retold
• More About Indexed Queue Architectures
• Column virtualization
• HASTE Re-retold