| Citation | PS | Other | |
|---|---|---|---|
| Graph Theory Papers | PS | Other | |
| Stack And Queue Layouts Of Directed Acyclic Graphs: Part I Lenwood S. Heath, Sriram V. Pemmaraju, Ann N. Trenk SIAM Journal on Computing (1996) | * | ||
| Stack And Queue Layouts Of Directed Acyclic Graphs: Part II Lenwood S. Heath, Sriram V. Pemmaraju SIAM Journal on Computing (1999) | * | ||
| Integer Linear Programming Approaches to Hierarchical Graph Drawing Ago Kuusik Ph.D. Thesis, University of Limerick (2000) | * | ||
| PipeRench Papers | PS | Other | |
| PipeRench: A Coprocessor for Streaming Multimedia Acceleration Seth Copen Goldstein, Herman Schmit, Matthew Moe, Mihai Budiu, Srihari Cadambi, R. Reed Taylor, Ronald Laufer ISCA (1999) | * | * | |
| PipeRench: A Reconfigurable Architecture and Compiler Seth Copen Goldstein, Herman Schmit, Mihai Budiu, Srihari Cadambi, Matt Moe, R. Reed Taylor Computer (2000) | * | * | |
| Managing Pipeline-Reconfigurable FPGAs Srihari Cadambi, Jeffrey Weener, Seth Copen Goldstein, Herman Schmit, Donald E. Thomas ACM/SIGDA International Symposium on Field Programmable Gate Arrays (1997) | * | * | |
| Incremental Reconfiguration for Pipelined Applications Herman Schmit IEEE Symposium on FPGAs for Custom Computing Machines (1997) | * | * | |
| Fast Compilation for Pipelined Reconfigurable Fabrics Mihai Budiu, Seth Copen Goldstein ACM/SIGDA International Symposium on Field Programmable Gate Arrays (1999) | * | * | |
| CPR: A Configuration Profiling Tool Srihari Cadambi, Seth Copen Goldstein IEEE Symposium on FPGAs for Custom Computing Machines (1999) | * | * | |
| PCI-PipeRench and the SWORDAPI: A System for Stream-based Reconfigurable Computing Ronald Laufer, R. Reed Taylor, Herman Schmit IEEE Symposium on FPGAs for Custom Computing Machines (1999) | * | * | |
| PipeRench Manual Matthew Myers, Kevin Jaget, Srihari Cadambi, Jeffrey Weener, Matthew Moe, Herman Schmit, Seth Copen Goldstein, Dan Bowersox Carnegie Mellon University (1998) | * | * | |
| A High-Performance Flexible Architecture for Cryptography R. Reed Taylor, Seth Copen Goldstein Cryptographic Hardware and Embedded Systems (1999) | * | * | |
| PipeRench: A Virtualized Programmable Datapath in 0.18 Micron Technology Herman Schmit, David Whelihan, Andrew Tsai, Matthew Moe, Benjamin Levine, R. Reed Taylor IEEE Custom Integrated Circuits Conference (2002) | * | ||
| Static Profile Driven Optimization of Digital Circuits Srihari Cadambi Ph.D. Thesis, Carnegie Mellon University (2000) | * | ||
| PipeRench Implementation of the Instruction Path Coprocessor Yuan Chou, Pazhani Pillai, Herman Schmit, and John Paul Shen MICRO (2000) | * | ||
| Fast and Efficient Place and Route for Pipeline Reconfigurable Architectures Srihari Cadambi, Seth C. Goldstein ICCD (2000) | * | ||
| Implementation of Near Shannon Limit Error-Correcting Codes using Reconfigurable Hardware Benjamin Levine, R. Reed Taylor, Herman Schmit FCCM (2000) | * | ||
| Tunable Fault Tolerance for Runtime Reconfigurable Architectures Steven K. Sinha, Peter M. Kamarchik, Seth C. Goldstein FCCM (2000) | * | ||
| Uncategorized Papers | PS | Other | |
| Active Messages: a Mechanism for Integrated Communication and Computation Thorsten von Eicken, David E. Culler, Seth Copen Goldstein, Klaus Erik Schauser 19th International Symposium on Computer Architecture (1992) | * | ||
| Executing a program on the MIT tagged-token dataflow architecture Arvind, R.S. Nikhil IEEE Transactions on Computers (1990) | * | ||
| Parallel Dispatch Queue: A Queue-Based Programming Abstraction To Parallelize Fine-Grain Communication Protocols Babak Falsafi, David A. Wood HPCA (1999) | * | ||
| Decoupled Access DRAM Architecture Alexander V. Veidenbaum, K. A. Gallivan | * | ||
| Design of a superscalar Processor Based on Queue Machine Computation Model Shusuke Okamoto, Hitoshi Suzuki, Atusi Maeda and Masahiro Sowa IEEE Pacific Rim Conferences, Computers and Signal Processing (1999) | * | ||
| Memory Decoupled Architectures and related issues – Guest Editor's Introduction Roberto Giorgi MEDEA Workshop (2000) | * | ||
| Operand Queue machine with multiple data queues Akifumi Tsukimori Master's Thesis, Carnegie Mellon University (2003) | * | ||
| Efficient Application Representation for HASTE: Hybrid Architectures with a Single, Transformable Executable Benjamin Levine, Herman Schmit Proc. IEEE Symposium on Field Programmable Custom Computing Machines (2003) | * | ||
| Scalable Data Management for Pipelined Reconfigurable FPGAs Jeffrey Weener Master's Thesis, Carnegie Mellon University (1998) | * | ||
| Augmenting a Microprocessor with Reconfigurable Hardware John Reid Hauser Ph.D. Thesis, Berkeley (2000) | * | ||
| ADAM: A Decentralized Parallel Computer Architecture Featuring Fast Thread and Data Migration and a Uniform Hardware Abstraction Andrew "bunnie" Huang Ph.D. Thesis, MIT (2002) | * | ||
| Data Flow on a Queue Machine Bruno Richard Preiss Ph.D. Thesis, University of Toronto (1987) | * | ||
| Functional Images Conal Elliot Chapter in The Fun of Programming (2003) | * | ||
| Optimized Hardware Synthesis for FPGAs Malay Haldar Ph.D. Thesis, Northwestern University (2001) | * | * | |
| Higher-order Concurrency John Hamilton Reppy Ph.D. Thesis, Cornell University (1992) | * | * | |
| Asynchronous Queue Machines with Explicit Forwarding Lennart Beringer Ph.D. Thesis, University of Edinburgh (2002) | * | * | |
| RS-FDRA: A Register Sensitive Software Pipelining Algorithm for Embedded VLIW Processors Cagdas Akturan, Margarida F. Jacome Proceedings of the ninth international symposium on Hardware/software codesign (2001) | * | ||
| SCALIP - A Scalable IP Solution for Pipelined Arrays with Limited Feedback Matthew Moe, Herman Schmit ASIC (2001) | * | ||
| Performance Analysis and Optimization of Asynchronous Circuits Steven M. Burns, Alain J.Martin Advanced Research in VLSI (2001) | * | ||
| Clock Rate versus IPC: The End of the Road for Conventional Microarchitectures Vikas Agarwal, M.S. Hrishikesh Stephen, W. Keckler, Doug Burger ISCA (2000) | * | * | |
| Digital receiver design using VHDL generation from data flow graphs Peter Zepter, Thorsten Grötker, Heinrich Meyr DAC (1995) | * | ||
| Software Technologies for Reconfigurable Systems Scott Hauck, Anant Agarwal Technical Report, Northwestern University (1996) | * | * | |
| Overcoming the Limitations of Conventional Vector Processors Christos Kozyrakis, David Patterson ISCA (2003) | * | ||
| A New Method for Functional Arrays Melissa E O'Neill, F. Warren Burton Journal of Functional Programming (1997) | * | ||
| Evaluation of the WM Architecture Wm.A. Wulf ISCA (1992) | * | * | |
| Why Functional Programming Matters John Hughes Computer Journal (1984) | * | * | |
| TAM- A compiler controlled threaded abstract machine D.E. Culler, S.C. Goldstein, K.E. Schauser and T. von Eicken Journal of Parallel and Distributed Computing (1993) | * | ||
| Beating the Averages Paul Graham | * | ||
| Version Management with CVS Per Cederqvist, et al | * | ||
| Evaluating the Use of Register Queues in Software Pipelined Loops Gary S. Tyson, Mikhail Smelyanskiy, Edward S. Davidson IEEE Transactions on Computers (2001) | * | * | |
| StreamIt: A Language for Streaming Applications William Thies, Michal Karczmarek, Saman Amarasinghe Computational Complexity (2001) | * | * | |
| Register Traffic Analysis for Streamlining Inter-Operation Communication in Fine-Grain Parallel Processors Manoj Franklin, Gurindar S. Sohi International Symposium on Microarchitecture (1992) | * | * | |
| An Instruction Set and Microarchitecture for Instruction Level Distributed Processing Ho-Seop Kim, James E. Smith (2002) | * | ||
| A Survey Of Stream Processing Robert Stephens Acta Informatica (1995) | * | * | |
| Using Queues for Register File Organization in VLIW Architectures Marcio Merino Fernandes, Josep Llosa, Nigel Topham Computer Science Group Report Series, University of Edinburgh (1997) | * | * | |
| A Scheme Shell Olin Shivers MIT (1994) | * | * | |
| HTML 4.01 Specification Dave Raggett, Arnaud Le Hors, Ian Jacobs, editors W3C | * | ||
| The Not So Short Introduction to LaTeX 2e Tobias Oetiker, Hubert Partl, Irene Hyna and Elisabeth Schlegl | * | ||
| The Objective Caml system release 3.06 Xavier Leroy (with Damien Doligez, Jacques Garrigue, Didier Rémy and Jérôme Vouillon) | * | * |