 Authored
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Coauthored
patents |
Patent
Applications |
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Authored
Patents |
Coauthored
patents |
Patent
Applications |
Floating-gate Semiconductor Structures, C. Diorio and T. Humes, U.S. Patent No. 6,965,142, issued November 15, 2005.
Differential Floating Gate Nonvolatile Memories, C. Diorio, U.S. Patent No. 6,950,342.
Method and apparatus for preventing overtunneling in pFET-based nonvolatile memory cells, C. Diorio, et al., U.S. Patent No. 6,853,583, issued February 8, 2005.
High-voltage CMOS-compatible capacitors, C. Diorio, et al., U.S. Patent No. 6,842,327, issued 11 January, 2005.
Method and Apparatus for Trimming a High- Resolution Digital-to-Analog Converter, J. Hyde, M. Figueroa, T. Humes, and C. Diorio, U.S. Patent No. 6,664,909, issued 16 December, 2003.
PMOS analog EEPROM cell, Chris Diorio and Carver Mead, U.S. Patent No. 6,452,835B1, issued 17 September, 2002.
pMOS EEPROM nonvolatile data storage, Chris Diorio and Carver Mead, U.S. Patent No. 6,144,581, issued 7 November, 2000.
Semiconductor structure for long-term learning, Chris Diorio and Carver Mead, U.S. Patent No. 6,125,053, issued 26 September, 2000.
Hole impact-ionization method of hot-electron injection and four-terminal pFET semiconductor structure for long-term learning, Chris Diorio, Paul Hasler, Bradley A. Minch, and Carver Mead, U.S. Patent No. 5,990,512, issued 23 November, 1999.
Method for implementing a learning function, Chris Diorio, Paul Hasler, Bradley A. Minch, and Carver Mead, U.S. Patent No. 5,914,894, issued 22 June, 1999.
A pMOS analog EEPROM cell, Chris Diorio and Carver Mead, U.S. Patent No. 5,898,613, issued 27 April, 1999.
A three-terminal silicon synaptic device, Chris Diorio, Paul Hasler, Bradley A. Minch, and Carver Mead, U.S. Patent No. 5,825,063, issued 10 October, 1998.
A semiconductor structure for long-term learning, Chris Diorio, Paul Hasler, Bradley A. Minch, and Carver Mead, U.S. Patent No. 5,627,392, issued 6 May, 1997.
Autozeroing Floating-Gate Amplifier, W.T. Colleran, T.E. Humes, and C.J. Diorio, U.S. Patent No. 6,958,646, issued October 25, 2005.
An autozeroing floating-gate amplifier, Bradley A. Minch, Paul Hasler, Chris Diorio, and Carver Mead, U.S. Patent No. 5,986,927, issued 16 November, 1999.
An autozeroing floating-gate amplifier, Bradley A. Minch, Paul Hasler, Chris Diorio, and Carver Mead, U.S. Patent No. 5,875,126, issued 23 February, 1999.
A noise-reducing technique for phase-locked loops,
Chris Diorio, utility patent application submitted to the U.S. Patent Office
on 4 March, 1998.