Gaetano Borriello's current and past students
Current Graduate Students
- Adrienne Andrew
- Harlan Hile: TBD
- Jong Hee Kang: Ubiquitous Broadcast Computing
- Lillie Kittredge
- Jonathan Lester (co-advised with Blake Hannaford): Embedded Statistical Inference for Human Activity Recognition
- Alan Liu: TBD
- Evan Welbourne:
TBD
Ph.D. Graduates
- Sushant Jain (2005): Routing in Delay-Tolerant Networks
- Kurt E. Partridge (2005): Using Attention-Correlated Communications to Associate Users and Devices
- Jeffrey R. Hightower (2004): The Location Stack
- Kenneth J. Hines (2000): Coordination-centric Debugging for
Heterogenous Distributed Embedded Systems
- Ross B. Ortega (2000): Communication Synthesis and Interface
Synthesis for Embedded Systems
- Pai H. Chou (1998): Control Composition and Synthesis of
Distributed Real-Time Embedded Systems
- Suzanne Bunton (1996, co-advised with Richard Ladner): On-Line
Stochastic Processes in Data Compression
- Elizabeth A. Walkup (1995): Optimization of Linear Max-Plus
Systems with Application to Timing Analysis
- Scott A. Hauck (1995, co-advised with Carl Ebeling): Multi-FPGA
Systems
- Tod T. Amon (1993): Specification, Simulation, and Verification
of Timing Behavior
M.S. Graduates
- Harlan Hile (2004): Microbiology Tray and Pipette Tracking as a
Proactive Tangible User Interface
- Adam MacBeth (2001): An Auto-configuring Service Discovery System
- Stefan Sigurdsson (2001): Sensor Configuration in Labscape
- Daniel Lloyd (2001): The Orb: Highly Interoperable Wireless
Storage
- Michael Esler (1999): A Lightweight Proxy for Connecting
Low-Power and Legacy Devices to Jini Networks
- Ian MacDuff (1997): Hardware/Software Tradeoffs in Embedded
Systems: A Case Study
- Soha Hassoun (1993): Improving State Assignment for Two-Level
Programmable Logic Devices
- Daniel Miles (1993): A Task Allocator for Real-Time
Multi-Processor Simulations
- Christopher Hebert(1992): Parallel Programming/Partitioning for
Unit-Delay Logic Simulation
- Henrik Hulgaard (1991): Testing Asynchronous Circuits
- Sitaram Raju (1990): Timing Optimization in Multi-Phase
Sequential Logic
- Gerald Carson (1990): A Testable CMOS Asynchronous Counter
gaetano@cs.washington.edu
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