Computer Architecture at the UW

This is an overview of computer architecture research at the University of Washington. There are also pages about other CSE research and about adding bibliographic entries to this page.

Benchmarks

• A set of multithreaded benchmarks that run under PRESTO.

Interconnection Architectures and Routing

• The Chaotic Routing Project. Chaotic Routing is a non-minimal, adaptive and fault-tolerant routing for multicomputer architectures. Information is available about the people, publications, and simulator, as well as related work and analysis of other routing schemes.
• Design and Evaluation of a Subblock Cache Coherence Protocol.
• The Meerkat Multicomputer a bus array multicomputer.
• A Multi-Level Hierarchical Cache Coherence Protocol for Multiprocessors.
• The Proteus parallel computer network architecture.

Memory Consistency

• A Performance Study of Memory Consistency Models.
• On Synchronization Patterns in Parallel Programs.
• Relaxed Consistency and Synchronization in Parallel Processors.

Memory Hierarchy Performance

• A home page on memory hierarchy performance.

Multithreading

• Impact of Sharing-Based Thread Placement on Multithreaded Architectures.
• The Effectiveness of Multiple Hardware Contexts.
• Simultaneous Multithreading Project Home Page.

Prefetching and Instruction Scheduling

• Balanced Scheduling: Instruction Scheduling When Memory Latency is Uncertain.
• Data Prefetching for High-Performance Processors.
• Effective Cache Prefetching on Bus-Based Multiprocessors.
• Limitations of Cache Prefetching on a Bus-Based Multiprocessor.
• The Marion System of Retargetable Instruction Scheduling and Code Generation.
• Reducing Memory Latency via Non-blocking and Prefetching Caches.

• Survey of simualtion and tracing tools
• A Comparative Study of Conservative And Optimistic Trace-Driven Simulations.
• The Validity of Trace-Driven Simulation for Multiprocessors.
• Optimistic Trace-Driven Simulation.
• A Parallel Trace-Driven Simulator: Implementation and Performance.
• Shade: A Fast Instruction-Set Simulator for Execution Profiling. A fast extensible cross-machine simulator that collects all sorts of tracing information.
• Techniques for Efficient Inline Tracing on a Shared-Memory Multiprocessor. MPtrace: design, implementation, performance and how to get it.
• Some Efficent Architecture Simulation Techniques: how to do fast processor simulation. See The Meerkat Multicomputer for extensions that simulate the running time and multiple processors.

Virtual Memory

• Architectural Support for Single Address Space Operating Systems

Other places to look

• Microprocessor compendiums courtesey of Cera
  • Chip-specific
  • Micro information
• The UW's ongoing work in Dependable Parallel Computers and Networks
• The UW's ongoing work in parallel compilers (compilers to exploit parallel machines).
• A computer architecture home page that includes information on work being done at many sites, calls for papers, processor manuals, and bibliographies. An excellent place to look, prepared by the University of Wisconsin-Madison Computer Sciences Department (one of many other UW's !-)
• Computers and Emulation: A page on the history and practice of computers and lists lots of system emulators.
• The CPU Info Center, with frequently updated announcements, news, SPEC data, technical reports, and so on. Courtesey of Tom Burd.
• Hints for clear writing, courtesy of Mark Leone.