By Craig Anderson and Jean-Loup Baer.

ABSTRACT

In order to meet the computational needs of the next decade, shared-memory processors must be scalable. Though single shared-bus architectures have been successful in the past, limited bus bandwidth restricts the number of processors that can be effectively put on a single bus machine. One architecture that has been proposed to solve the limited bandwidth problem connects processors using a tree hierarchy of buses. In this paper, we present a tool to study a hierarchical bus based shared-memory system. We show that there is a need for transitional states in the cache coherence protocol that are not necessary in single bus architectures. We also give several examples of the protocol in action. Finally, we conclude with some preliminary results, and some examples of how the protocol and architecture could be made more efficient.

@techreport{Andersonb92,
    author = "{Anderson, C. and J.-L. Baer}",
    title = "A Multi-Level Hierarchical Cache Coherence Protocol
             for Multiprocessors",
    institution = "University of Washington",
    number = "92-10-04",
    year = "1992"
}