Codes/CASHE '98 Advance Program

Sunday, March 15

19:00-22:00 - Reception

Monday, March 16

07:45-08:45 - Registration & Breakfast Buffet

08:45-09:00 - Opening Session

• Welcome from chairs
• Organization of program

09:00-10:20 - Session 1: System Level Modeling

Papers:

• An Analysis-based Approach to Composition of Distributed Embbeded Systems
  P. Chou and G. Borriello
• Combining Multiple Models of Computation for Scheduling and Allocation
  D. Ziegenbein, R. Ernst, K. Richter, J. Teich and L. Tiele
• Modeling Reactive Systems in Java
  C. Passerone, R. Passerone, C. Sansoe, J. Martin, A. Sangiovanni-Vincentelli and R. McGeer

Posters:

• A Unified Component Modeling Approach for Performance Estimation in Hardware/Software Codesign
  J. Grode and J. Madsen

10:20-10:40 - Break

10:40-12:00 - Session 2: Partitioning

Papers:

• Energy-Conscious HW/SW-Paritioning of Embedded Systems: A Case Study on an MPEG-2 Encoder
  J. Henkel and Y. Li
• Hipart: A New Hierarchical Semi-Interactive HW/SW Partitioning Approach with Fast Debugging for Real-Time Embedded Systems
  T. Hollstein, J. Becker, A. Kirschbaum, M. Glesner
• Towards Interprocess Communication and Interface Synthesis for a Heterogeneous Real-Time Rapid Prototyping Environment
  F. Fischer, A. Muth, Georg Färber

Posters:

• A Grouping Partitioning Technique with Automatic Criterion Selection for the Codesign Process
  J.A. Maestro and D. Mozos

12:00-13:30 - Lunch

13:30-14:50 - Session 3: Communication and Interface Synthesis

Papers:

• Domain-Specific Interface Generation from Dataflow Specifications
  M. Eisenring and J. Teich
• Communication Synthesis and HW/SW Integration for Embedded System Design
  G. Gognat, M. Auguin, L. Bianco, A. Pegatoquet
• Communication Estimation for Hardware/Software Codesign
  P. Voigt Knudsen and J. Madsen

Posters:

• Realizability and Synthesis of Interface Controllers
  A. El-Aboudi, E.M. Aboulhamid, E. Cerny

14:50-15:05 - Break

15:05-17:05 - Invited Talks

• FlexWare: A Flexible Hardware/Software Development Encironment and its Application to Consumer Multimedia Product Designs
  Dr. Pierre. Paulin, SGS-Thomson Microelectronics, Grenoble, France
• Smartbadges: A Wearable Computer and Communication System
  Prof. Dr. Gerald Q. Maguire Jr., Royal Institute of Technology, Stockholm, Sweden
  Dr. Mark T. Smith, Hewlett-Packard Research Laboratories, Palo Alto, California, USA
  Dr. H.W. Peter Beadle, University of Wollongong, Wollongong, Australia

Tuesday, March 17

08:00-09:00 - Breakfast Buffet

09:00-10:20 - Session 4: Cosimulation

Papers:

• Software Timing Analysis Using HW/SW Cosimulation and Instruction Set Simulator
  J. Liu, M. Lajolo, A. Sangiovanni-Vincentelli
• Optimistic Distributed Timed Cosimulation Based on Thread Simulation Model
  S. Yoo and K. Choi
• Fast Dynamic Analysis of Complex HW/SW Systems based on Abstract State Machine Models
  G. Del Castillo and W. Hardt

Posters:

• A High Level Object Cosimulation Technique for Real-Time HW/SW Systems
  O. Pasquier and J.P. Calvez
• Integrated System Level Simulation Techniques for the Design of Embedded Systems
  U. Freund, V. Zerbe, G. Schorcht
• Virtual Prototyping, a Case Study in Dataflow Oriented Codesign
  H. Holten-Lund, M. Lütken, J. Madsen, S. Perdersen
• Object-Oriented Design of ATM Switch Hardware in a Telecommunication Network Simulation Environment
  G. Post, A. Müller, R. Schoenen

10:20-10:40 - Break

10:40-12:00 - Session 5: Scheduling

Papers:

• A Path Analysis based Partitioning for Time Constrained Embedded Systems
  L. Bianco, M. Auguin, G. Gogniat, AL Pegatoquet
• Schedulability Analysis of Heterogeneous Systems for Performance Message Sequence Chart
  F. Slomka, J. Zant, L. Lambert
• TGFF: Task Graphs for Free
  R.P. Dick, D. L. Rhodes, W. Wolf

Posters:

• Rapid Prototyping of Embedded Systems Running Concurrent Applications with Task-level Dynamics: Hardware Architecture Selection, Mapping, and Real-time Scheduler Selection
  A. Kalavade and P. Moghé
• Process Scheduling for Performance Estimation and Synthesis of Hardware/Software Systems
  P. Eles, K. Kuchcinski, Z. Peng, A. Doboli, P. Pop
• An RTOS Simulator with Synchronous Semantics
  E. M. Sentovich
• Quasi-Static Scheduling of Free-Choice Petri Nets
  M. Sgroi, L. Lavagno, A. Sangiovanni-Vincentelli

12:00-13:30 - Lunch

13:30-14:50 - Session 6: Case Studies

Papers:

• A Hardware/Software Prototyping Environment for Dynamically Reconfigurable Embedded Systems
  J. Fleischmann, K. Buchenrieder, R. Kress
• Hardware/Software Codesign of an ATM Network Interface Card: aCase Study
  J.M. Daveau, G. Marchioro, A.A. Jerraya
• A Case Study on Modeling Shared Memory Access Effects during Performance Analysis of HW/SW Systems
  M. Lajolo, A. Raghunathan, S. Dey, L. Lavagno, A. Sangiovanni-Vincentelli

Posters:

• Hardware-Software Run-Time Systems and Robotics: A Case Study
  V.J. Mooney III, D. Ruspini, O. Khatib, G. De Micheli
• A Case Study in Heterogeneous Implementation of Automotive Real-Time Systems
  J. Axelsson
• Reconfigurable Processing as a Target Architecture for Codesign
  W. Fornaciari, L. Pozzi, M.G. Sami

14:50-15:05 - Break

Group Discussion: 15:05-17:00

18:00-22:00 - Workshop Dinner at the Boeing Museum of flight

Wednesday, March 18

08:00-09:00 - Breakfast Buffet

09:00-10:20 - Session 7: System on Chip

Papers:

• The Construction of a Retargetable Simulator for an Architecture Template
  B. Kienhuis, E. Deprettere, K. Vissers, P. von der Wolf
• HDL Code Restructuring Using Timed Decision Tables
  J. Li and R. Gupta
• Instruction Subsetting: Trading Power for Programmability
  W.E. Dougherty, D.J. Pursley, D.E. Thomas

Posters:

• Building an Executing Y-charts for Heterogeneous System Design
  P. van der Wolf and K. Vissers
• An Embedded Software Programming Language for Application Specific Datapath Width Processors
  A. Inoue, H. Tomiyama, T. Shimizu, H. Kanbara, H. Yasuura

10:20-10:40 - Break

10:40-12:00 - Session 8: System Level Modeling

• RECOD: A Retiming Heuristic To Optimize Resource And Memory Utilization in HW/SW Codesigns
  K.S. Chatha and R. Vemuri
• Task Level Memory Hierarchy for Low Power Real-Time Systems
  Y. Li, W. Wolf, J. Henkel
• Memory Size Estimation for Multimedia Applications
  P. Grun, F. Balasa, N. Dutt

12:00-13:30 - Lunch

13:30-15:00 - Closing Session

• Five minute statements by attendees
• Closing remarks