Dynamic linking is again becoming common and processor pipeline depths are increasing. These factors make it worth retuning dynamic linker implementations. This note examines the current dynamic linking scheme used by System V.4 running on SPARC V8 processors and shows four alternative implementations that can improve the performance of calls to dynamically-linked functions. Improvements come from reducing the number of instructions that must be executed to perform a call; from reducing the dynamically cached size of the linkage table ; and by performing control transfers using instruction immediates instead of indirecting off of a register. In the best case, the overhead of calling a dynamically linked instruction is reduced from four instructions with a register indirect to a single instruction and no register indirect. The paper also discusses issues and techniques that may be useful for other systems that perform dynamic using similar techniques. This note also briefly considers dynamic relinking.
%A David Keppel
%A Stephen Russell
%T Faster Dynamic Linking for SPARC V8 and System V.4
%I University of Washington
%R UWCSE 93-12-08
%D 1993
%X The dynamic linker code for SV.4 ABI takes 4 instruction times for
each dynamically-linked call/return. Alternative schemes are
proposed in which the time is reduced to as little as one instruction
time and two instruction words of overhead. Some use jumps to an
immediate address rather than indirecting through a register,
improving the performance on deep-pipeline machines. Also breifly
discusses dynamic unlinking and relinking.
@techreport{KR:93,
author={David Keppel and Stephen Russell},
title={Faster Dynamic Linking for SPARC V8 and System V.4},
number={UWCSE 93-12-08},
institution={University of Washington Department of Computer
Science and Engineering},
month={December},
year={1993}
}