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Department of Computer Science and Engineering University of Washington

Motivation

Scientific computing and streaming data applications often exhibit high levels of micro-parallelism and are at the forefront of computer science research and industry development. Examples of streaming data applications are network packet processing, video, voice, graphics, and digital signal processing. Scientific applications such as DNA sequence analysis and protein folding exhibit abundant micro-parallelism and have an insatiable appetite for processing power. These programs are typically very complex, so despite the abundance of micro-parallelism, if performance permits, they are often implemented on general-purpose sequential processors. When traditional sequential processors fail to perform adequately, industry and academia have either augmented or replaced these processors with spatial computing fabrics such as dedicated hardware, FPGAs, graphics processors, digital signal processors, reconfigurable processors, or parallel processor systems. The cost of using either spatial fabrics or parallel processors is that programming the application is much more difficult. For many of these micro-parallel applications, spatial fabrics can offer a tremendous advantage in performance, power efficiency and computational density. Nonetheless, the general difficulty in programming spatial fabrics has hindered their widespread adoption. For this reason we intend to develop a reconfigurable spatial fabric that integrates with a sequential processor and supports both an execution model and a language that programmers and compilers can use to effectively take advantage of micro-parallel execution.

Introduction to the Hybrid Micro-Parallel Architecture

The hybrid micro-parallel (HMP) architecture is an effort to create a processor family that excels at executing micro-parallel applications and maintains an ease of programming similar to that of a general-purpose sequential processor. To achieve our goals we are focusing our efforts on several areas:

• Defining a new abstract model, the HMP type architecture, for this class of machines.
• Augmenting a traditional sequential processor for interaction with a micro-parallel engine.
• Exploring the communication and control requirements for integrating a micro-parallel engine with a sequential processor.
• Designing a coarse-grained reconfigurable spatial fabric that is tailored for micro-parallel execution.

HMP Type Architecture

The hybrid micro-parallel (HMP) type architecture represents a class of machine that combines a general-purpose sequential processor with a specialized spatial fabric, i.e. a micro-parallel engine. The goal of the HMP type architecture is to simplify the task of programming these micro-parallel engines.

Augmenting a sequential processor

For the HMP architecture, we require a general-purpose sequential processor. At this point in time, we are using standard RISC architectures and adding support for the following features:

• Streaming memory engines
• Instructions to push and pull data into the micro-parallel engine
• Instructions to start and stop the micro-parallel engine

With preliminary work on the HMP type architecture completed, our group’s research has focused on both the development of a programming language and an emulation system for the HMP architecture. The emulation environment is using a Xilinx Virtex-II Pro FPGA with embedded MicroBlaze soft-core microprocessor. The purposes of my emulation environment are to profile and benchmark applications and to serve as a tool for the architectural exploration, modeling, and development of the REMAP micro-parallel engine.

REMAP: A Reconfigurable Engine for Micro-parallel Application Programming

We are developing a micro-parallel engine as a component of a hybrid micro-parallel type architecture. This micro-parallel engine, REMAP, will be a specialized reconfigurable spatial fabric that is optimized for executing the micro-parallel kernels of computationally intensive applications.

The thrust of the REMAP architecture will be to meet several key design goals.

1. Integrate with a sequential processor to offload computation of micro-parallel sections of an application. Callahan et al. explored this design space for fine-grained configurable architectures with the GARP project. REMAP will build on this work, and will focus on extending it to apply to coarse-grained micro-parallel engines.
2. Support a programming model that is a reasonable target for both a programmer and a compiler.
3. Provide effective resource virtualization, analogous to that provided by a traditional microprocessor, and derived from configurable architectures such as PipeRench, RaPiD, and SCORE.
4. Utilize a coarse-grained configurable datapath to provide an efficient solution for implementing a wide range of micro-parallel application kernels.

Several previous research efforts have addressed many of these points individually. One contribution of this work will be to synthesize these ideas in the context of a single micro-parallel architecture. This work should also lead to improved resource virtualization, which is an important issue for flexible micro-parallel engines, and it should yield a coarse-grained datapath with support for a fine-grained control plane that supports dynamic and static control. By combining these properties into a micro-parallel engine and integrating it with a sequential processor, we intend to contribute to the creation of a new class of processors that have an elegant and straightforward programming model yet will take advantage of the micro-parallelism associated with many scientific and streaming data applications.