Papers by projects in the Laboratory for Integrated Systems

This file is not for reference in Web documents. This is intended as a database only. Entries should be copied to the pages where they are needed. Look in the file papers.bib for the bibtex entries for these papers.
C. Ebeling, G. Borriello, S. Hauck, D. Song, and E. A. Walkup.
"Triptych: A New FPGA Architecture", Oxford Workshop on Field-Programmable Logic and Applications Oxford, September, 1991. Also appearing in W. Moore, W. Luk, Eds., FPGAs, Oxford: Abingdon EE&CS Books, pp. 75-90, 1991.

E. A. Walkup, S. Hauck, G. Borriello, and C. Ebeling.
"Routing-directed Placement for the Triptych FPGA", ACM/SIGDA Workshop on Field-Programmable Gate Arrays, Berkeley, February, 1992.

S. Hauck, G. Borriello and C. Ebeling.
"TRIPTYCH: An FPGA Architecture with Integrated Logic and Routing", Advanced Research in VLSI and Parallel Systems: Proceedings of the 1992 Brown/MIT Conference, pp. 26-43, March, 1992.

S. Hauck, G. Borriello, S. Burns and C. Ebeling.
"Montage: An FPGA for Synchronous and Asynchronous Circuits", 2nd International Workshop on Field-Programmable Logic and Applications, Vienna, August 1992. Also appearing in H. Grunbacher, R. W. Hartenstein, Eds., Field-Programmable Gate Arrays: Architectures and Tools for Rapid Prototyping, Berlin: Springer-Verlag, pp. 44-51, 1993.

Pai Chou, Ross Ortega, Gaetano Borriello,
"Synthesis of the Hardware/Software Interface in Microcontroller-Based Systems,"
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Santa Clara, CA, November 1992. pp.488-495.

S. Hauck.
"Asynchronous Design Methodologies: An Overview", to appear in Proceedings of the IEEE, Vol. 83, No. 1, January 1995. Also appearing as University of Washington, Dept. of C.S.&E. TR #93-05-07, 1993.

S. Hauck, G. Borriello, C. Ebeling.
"Springbok: A Rapid-Prototyping System for Board-Level Design", ACM/SIGDA 2nd International Workshop on Field-Programmable Gate Arrays, Berkeley, February, 1994.

S. Hauck, G. Borriello, C. Ebeling.
"Mesh Routing Topologies for FPGA Arrays", ACM/SIGDA 2nd International Workshop on Field-Programmable Gate Arrays, Berkeley, February, 1994.

S. Hauck, G. Borriello.
"Pin Assignment for Multi-FPGA Systems (Extended Abstract)", IEEE Workshop on FPGAs for Custom Computing Machines, pp. 11-13, April, 1994.

Pai Chou, Gaetano Borriello,
"Software Scheduling in the Co-Synthesis of Reactive Real-Time Systems,"
in Proceedings of the Design Automation Conference, San Diego, CA, June 1994. pp.1-4.

Pai Chou, Elizabeth Walkup, Gaetano Borriello,
"Scheduling Issues in the Co-Synthesis of Reactive Real-Time Systems,"
IEEE Micro , August 1994. pp.37-47. Also appeared as Technical Report 94-09-04 , Dept. of Computer Science and Engineering, University of Washington, Seattle, WA 98195.

S. Hauck, S. Burns, G. Borriello, C. Ebeling.
"An FPGA For Implementing Asynchronous Circuits", IEEE Design & Test of Computers, Vol. 11, No. 3, pp. 60-69, Fall, 1994.

S. Hauck, G. Borriello, C. Ebeling.
"Mesh Routing Topologies for Multi-FPGA Systems", International Conference on Computer Design, pp. 170-177, 1994.

S. Hauck, G. Borriello, S. Burns, C. Ebeling.
"Field-Programmable Gate Array for Synchronous and Asynchronous Operation", U.S. Patent 5,367,209, issued November 22, 1994.

S. Hauck, G. Borriello.
"Pin Assignment for Multi-FPGA Systems", submitted to Design Automation Conference, 1995. Also appearing as University of Washington, Dept. of C.S.&E. TR #94-04-01, 1994.

S. Hauck, G. Borriello.
"Logic Partition Orderings for Multi-FPGA Systems", to appear in ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Monterey, CA, February, 1995.

S. Hauck, G. Borriello.
"An Evaluation of Bipartitioning Techniques", to appear in Chapel Hill Conference on Advanced Research in VLSI , March, 1995.

Pai Chou, Gaetano Borriello,
"Interval Scheduling: Fine Grained Code Scheduling for Embedded Systems,"
in Proc. Design Automation Conference, June 1995, San Francisco, CA. pp 462-467.

J. A. Brzozowski, S. Hauck, C.-J. H. Seger.
"Chapter 15: Design of Asynchronous Circuits", to appear in J. A. Brzozowski, C.-J. H. Seger. Asynchronous Networks, Springer-Verlag, 1995.

G. Borriello, C. Ebeling, S. Hauck, S. Burns.
"The Triptych FPGA Architecture", to appear in IEEE Transactions on VLSI Systems.

C. Ebeling, L. McMurchie, S. Hauck, S. Burns.
"Mapping Tools for the Triptych FPGA", submitted to IEEE Transactions on VLSI Systems.

S. Hauck, G. Borriello, C. Ebeling.
"Mesh Routing Topologies for Multi-FPGA Systems", submitted to Journal of VLSI Signal Processing.

S. Hauck, G. Borriello, C. Ebeling.
"Achieving High-Latency, Low-Bandwidth Communication: Logic Emulation Interfaces".

Pai H. Chou, Ross B. Ortega, Gaetano Borriello.
"Interface Co-Synthesis Techniques for Embedded Systems", in Proceedings of ICCAD'95, San Jose, CA USA. pp. 280-287.

Pai H. Chou, Ross B. Ortega, Gaetano Borriello.
"The Chinook Hardware/Software Co-Synthesis System", in Proceedings of the International Symposium on System Synthesis, Cannes, France, September 1995.

Larry McMurchie, Carl Ebeling.
"PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs", in FPGA '95, February 1995.

Pai H. Chou, Ross B. Ortega, Gaetano Borriello.
"The Chinook Hardware/Software Co-Synthesis System", submitted to Transactions on VLSI.

Darren C. Cronquist, Steven M. Burns.
"Synthesis and Analysis of a Delay-Insensitive Folded FIFO", TAU '95.

Soha Hassoun, Carl Ebeling.
"Architectural Retiming: An Overview", TAU '95.

Darren C. Cronquist, Larry McMurchie.
"Emerald - An Architecture-Driven Tool compiler for FPGAs", in FPGA '96, February 1996.

Steven M. Burns.
"General Conditions for the Decomposition of State Holding Elements", submitted to Async'96.

Soha Hassoun, Carl Ebeling.
"Architectural Retiming: Pipelining Latency-Constrained Circuits", submitted to DAC'96.

Carl Ebeling, Darren C. Cronquist, Paul Franklin.
"RaPiD - Reconfigurable Pipelined Datapath", in The 6th International Workshop on Field-Programmable Logic and Applications, 1996.

Carl Ebeling, Darren C. Cronquist, Paul Franklin, Chris Fisher.
"RaPiD - A Configurable Computing Architecture for Compute-Intensive Applications", Technical Report UW-CSE-96-11-03, November 1996.

Ken Hines.
"Pia: A Framework for Embedded System Co-simulation with Dynamic Communication Support", Technical Report UW-CSE-96-11-04, November 1996.

Ken Hines, Gaetano Borriello.
"Dynamic Communications Models in Embedded System Co-simulation", submitted to DAC'97.

Ken Hines, Gaetano Borriello.
"Optimizing Communication in Embedded System Co-simulation", submitted to Codes/CASHE'97.

Pai Chou, Gaetano Borriello.
"Software Architecture Synthesis for Retargetable Real-Time Embedded Systems", submitted to Codes/CASHE'97.

Ross Ortega, Gaetano Borriello.
"Communication Synthesis for Embedded Systems with Global Considerations", submitted to Codes/CASHE'97.