RaPiD

Research on Coarse-Grained Adaptable Architectures

Department of Computer Science and Engineering
The University of Washington

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Defining Coarse-Grained Configurable Architectures
Compiling to Coarse-Grained Configurable Architectures
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Introduction

Our research is focussed on defining coarse-grained adaptable architectures that solve the performance/power/price constraints posed by mobile/embedded systems platforms.  These platforms are being driven by multimedia applications, advanced user interfaces that include speech recognition technologies, and high bandwidth wireless communication which impose severe performance and power constraints that can be met only by ASIC technology.  Our goal is to show that coarse-grained adaptable architectures can provide much of the functionality currently provided by ASIC components, with efficiently close to that of ASICs and programmability approaching that of processors.

Our research focusses on two closely related topics:

Defining efficient coarse-grained adaptable architectures

The RaPiD architecture is a general coarse-grained reconfigurable architecture that we have developed over the past few years.  We have shown that RaPiD is effective for a wide range of problems in the signal and image processing domain.  RaPiD is currently programmed using Rapid-C, a language that allows the programmer to schedule computations to the architecture while hiding most of the details of the architecture.  The Rapid-C compiler generates and optimizes the configured control circuits for the program.  Rapid-C programs are simulated by first synthesizing them into Verilog. We have also build an emulator board which allows compiled Rapid-C programs to be run at a clock rate of 25MHz.  A large 64MByte streaming memory system as well as streaming interfaces to external devices allows real application prototypes to be built.

Compiling high-level languages to coarse-grained adaptable architectures

Our research is now focussed on developing compiler techniques for compiling high-level language descriptions to general coarse-grained adaptable architectures.  Although Rapid-C provides a nice abstraction of the architecture, the programmer is still responsible for all the scheduling of data and operations in the datapath.  Our goal is to combine VLIW compiler techniques to generate control-dataflow graphs that are then scheduled to a Rapid array using place and route techniques that are more typical of physical design tools.